Current Limiting Diodes

By Harvey Morehouse



Contents:



Current Limiting Diodes: Part 1


About the writer: Harvey Morehouse is an EE contractor/consultant with many years of experience using circuit analysis programs. His primary activities are in Reliability, Safety, Testability and Circuit Analysis. He may be reached at harvey.annie@verizon.net. Simple questions regarding my articles for which I know the answer are free. Complex questions, especially where I am ignorant of the answers, are costly!!!

Summary: Current Limiting Diodes, also called Current Regulating Diodes or Constant Current Diodes, are devices that act like a dual of a zener diode. That is, over a range of applied voltage they will exhibit a constant current characteristic. Refer to reference 1.

Shorting the Gate to Source connections of a JFET, with the applied voltage between the Drain and Source, usually creates such devices.

CLD Device Performance:

A characteristic curve of such a device is shown in Figure 1 following:


Figure 1
Typical CLD Device DC Characteristics

From Figure 1 it can be seen that the device performs as a constant current generator after about some voltage level of more is applied from anode (drain) to cathode (source) of the device until breakdown occurs. Whereas, in the reverse direction it operates as a forward biased diode.

(Central Semiconductor provides models for their CLD devices in Reference 2, which BEIGEBAG™ should incorporate into their database. However, we will be creating our own behavioral device model later that may be used to model other devices from other manufacturers, or during development when the exact device characteristics required or the device to be used are not determined.)

A portion of the Central Semiconductor Datasheet for the CCLHM080 through CCLHM150 devices is shown here as Figure 2.


Figure 2
Datasheet excerpt

From Figure 2, looking at the data for the CCLMN150 device, we can see that the points/regions on the curve of Figure 1 can be identified. Clearly, for the most part, a piecewise linear model would be appropriate if we did not know the specific JFET part used to create the device.

Now, in effect, what we wish to do is to create a part similar to that shown in Figure 3 following:


Figure 3
Effective equivalent circuit

Central Semiconductor shows a behavioral type circuit as shown in Figure 3. We see that there is a capacitive component, that varies from about 4 to 10 picofarads dependent on the specific device. Let us make a JFET device based model and examine how it behaves. This is shown in Figure 4 following:


Figure 4
JFET test circuit

Here we are using the B2SPICE™ generic 'n' channel JFET device. V1 produces a 0 - 100V ramp. Am1 measures the current. A graph of the circuit is shown in Figure 5 following:


Figure 5
JFET test circuit graph

Here we can see in the I(Am1) blue trace that the device current initially rises until it reaches 0.4 ma, and it remains constant to 6 decimal places throughout the remaining portion of the input ramp. Naturally enough, the v3 voltage also is constant.

Now it is not known if the JFET model accurately models the pinch-off behavior of a real JFET, the basis of CLD device operation. Certainly for some JFET devices in the library the output does not seem to be well behaved. Moreover, with a 1000 volt input ramp, the breakdown region is not evidenced.

Expanding the graph shows that the constant current region is reached at about 2V, somewhat near the threshold level shown in Figure 2 as VK, and the current is roughly in the ballpark.

However, the problem remains in the selection JFET parameters that will produce the performance we wish to achieve. Without some work, either to analytically determine how to modify the JFET parameters, or trial and error selection, or knowledge of the specific JFET part used to create a CLD device. Hopefully, the good guys at B2SPICETM will see fit to include the Central Semiconductor CLD devices into their library at the next database update.

The devices should be added into the ACTIVE/DIODE/CURRENT REGULATOR category of the parts database, which is a new category you must create.

The listing is available at http://www.centralsemi.com/spicemodels/spicedirectory.aspx.

Interestingly enough, the library listing for the CCLH1500 device datasheet shows a 50-volt rating for the POV while the library device lists 100V. The difference doubtless reflects a package difference/thermal consideration as the datasheet POV value is at a lead temperature of 75 degrees C, and a peak device power of 800 mw.

With a nominal current value of 15ma, and 50V this is 750mw. At a maximum device internal operating temperature of 200 degrees C, this leads to the conclusion that the thermal resistance from junction to lead is (200-75)/(750 mw) or about 167 degrees C per watt, which is not an unreasonable value.

Conclusions:

A CLD device is useful in creating a stable current source for a zener diode, and for other interesting purposes. Some application ideas are available in the references and in other articles at the Central Semiconductor WEB site.

References:

1. Central Semiconductor:
http://semiconductors.globalspec.com/LearnMore/Semiconductors/Discrete/Diodes/Current_Limiting_Diodes

2. Central Semiconductor, SPICE models and datasheet:
http://www.centralsemi.com/spicemodels/spicecld.aspx



Current Limiting Diodes: Part 2


Summary: Current Limiting Diodes, also called Current Regulating Diodes or Constant Current Diodes, are devices that act like a dual of a zener diode. That is, over a range of applied voltage they will exhibit a constant current characteristic. Refer to reference 1.

This article will discuss some of the uses and needs for CLD devices.

CLD Device Performance:

One of the primary needs for a current limiting device is in the generation of a precision voltage reference. Often one starts out with a circuit such as is shown in the following Figure 1.


Figure 1
Basic regulated voltage circuit

Figure 1 shows a very simple voltage regulation circuit. From this circuit we would expect that V1 would exhibit a current of about (40 -22)/1.44K amps, or 12.5 ma. R2 would draw about 22/22K amps or about 1 ma, hence the diode D1 should see a current of about 11.5 ma.

Performing a simulation reveals that the diode current is about 11.497 ma, the diode current is 11.497 ma, the zener voltage is 22.005 volts, and the supply current is 12.497ma. Close enough for government work.

Let us suppose now that there might be a DC voltage variation of the supply voltage of 1.0V. An AC sweep is performed on the circuit, and a transient V3 source of 1V is placed in series with V1, with a frequency of 10 Hz to minimize the effect of any reactive elements that might be present in the model elements. Performing a simulation on this circuit results in the graph of Figure 2 following.


Figure 2
Basic regulated voltage circuit transient AC test

Here we see the AC voltage across the zener diode as v1, approximately 9.59mv peak, and the zener diode current AC is approximately as 0.68675ma peak

An ac sweep was performed, and the results are shown in Figure 3 following.


Figure 3
Basic regulated voltage circuit transient AC sweep

Distressingly, variations in V1 are present to high frequencies. Let us add a 100u capacitor across the zener diode. The transient AC source was set to 1 HZ This results in the transient plot of Figure 4 following:


Figure 4
Basic regulated voltage circuit#2 transient AC

The AC output is about 9.585mv peak, not much change as might be expected. The AC sweep of this circuit is shown in Figure 5 following:


Figure 5
Basic regulated voltage circuit#2 AC sweep

For AC voltages there is a dramatic change. Here we see the low frequency rejection has been improved. At 10 Hz we have a rejection of -18 dB, which was previously about -0.5 dB. Can we do better?

Suppose we were to replace the single resistor R1 in Figure 1 with two resistors, R1 and R3. The 100uF capacitor would be connected at their junction to ground. The resistances of R3 would equal xR, and R1 would equal (1-x)*R, where R was 1.44K. Now were 'x' equal to 1, R1 would be zero and the capacitor would essentially connected across the source, and would have no AC effect.

Were x = 1, R3 would be zero and the capacitor would essentially be across the zener diode. However, as the zener diode incremental resistance is so low, the frequency must become large for capacitor impedance to equal the value of the zener diode incremental resistance. It seems that there might be some division of R between R1 and R3 that is optimal.

Now we could use calculus to determine this if we knew the zener diode incremental resistance. But being lazy, the circuit of Figure 6 following was prepared.


Figure 6
Regulated voltage circuit#3 transient circuit

In Figure 6 we use a vpot device U1 to allow the resistance to be varied between what would be resistors R1 (to the left) and R3 (to the right). The value of 'x' is equal to the voltage applied to the control terminals above the device.

Voltage source V4 provides a ramp as a control voltage (x) varying from zero to one volt. A graph of the circuit output is shown in Figure 7 following:


Figure 7
Regulated voltage circuit#3 transient test

Now this is interesting!! The capacitor C1 seems to be charging!! But why is this, you say?

Well, initially the equivalent R1 resistor was 1.44K and the output ripple was large. But the first half wave of the input sine wave was slightly larger than the second half wave, and so on till a minimum voltage was reached. The circuit is of course nonlinear. Also, as the resistors change, the DC drop across R1 and R3 equivalents also change with R1 equivalent dropping less and less DC voltage.

Some other effects occur, but here we are just concerned with the AC attenuation. From Figure 7 it is clear that the minimum ratio is somewhere between 0.2 and 0.9 for the values present in the circuit. We will choose a value of 'x' equal to 0.5 for convenience.

Now, using this value we get the circuit shown in Figure 8 following:


Figure 8
Regulated voltage circuit#4

Performing a transient test on this circuit we arrive at the graph shown in Figure 9 following:


Figure 9
Regulated voltage circuit#4 transient test

In Figure 9 the AC output voltage is 21uV peak!! Quite a dramatic decrease!! Performing an AC sweep we arrive at the graph shown in Figure 10following:


Figure 10
Regulated voltage circuit#4 AC test

The AC sweep of Figure 10 reveals the attenuation is about 48 dB at 10 Hz, confirming the effectiveness of this technique. But can we do even better? Consider the circuit shown in Figure 11 following:


Figure 11
CLD-zener circuit

A transient graph of the circuit is shown in Figure 12 following:


Figure 12
CLD-zener circuit transient graph

In figure 12 we see that the peak ac output voltage is about 11.4uV. And AC sweep was performed, and is shown in Figure 13 following:


Figure 13
CLD-zener circuit AC sweep graph

In Figure 13 we see an interesting picture. The AC attenuation starts at almost 99 dB and stays at more than 72 dB to one MHz. But the REALLY great thing is that large DC source voltage changes are greatly attenuated.

Conclusions:

In the preceding, a development was shown where starting with a rather simple DC voltage reference circuit, its performance was progressively improved in terms of noise rejection. This shows how for one application CLD devices can be very useful. Now this is just a small portion of the work required to validate the circuit performance. In a 'real world' design we would have to consider variations in the component device parameters as well as the input and loading variations, power and more.

But in many applications the actual current value of a particular CLD over production is not as important as its being a stable current output.

Some application ideas are available in the references and in other articles at the Central Semiconductor WEB site.

References:

  1. Central Semiconductor, SPICE models and datasheet:
    http://www.centralsemi.com/spicemodels/spicecld.aspx


Current Limiting Diodes: Part 3


Summary: Current Limiting Diodes, also called Current Regulating Diodes or Constant Current Diodes, are devices that act like a dual of a zener diode. That is, over a range of applied voltage they will exhibit a constant current characteristic. Refer to the previous articles on Current Limiting Diodes (Current Limiting Diodes and Current Limiting Diodes (part2):

This concluding article will discuss some of the uses and performance for CLD devices.

Extending CLD Device Performance:

One problem in using CLD devices (and zener/avalanche diodes for that matter) is the granularity and range of the allowable device currents (voltages). There are simple circuits that enable the current of a given CLD device to be increased. One is shown in Figure 1 following:


Figure 1
NPN CLD current booster

The schematic is taken from an article entitled "Boosting the Current Limit of Current Limiting Diodes" by Sze Chin, Central Semiconductor Corp. A link to this may be found at the bottom of the page:
http://www.centralsemi.com/engineering/index.aspx

There is a little derivation wherein it is shown that ideally the boosted current is approximately the CLD current multiplier by the ratio of R2/R1 plus 1. This is somewhat optimistic, as it is based on a perfect transistor.

A graph of the circuit output using a 2n3055 and R2 = 200 ohms is shown in Figure 2 following:


Figure 2
NPN CLD current booster graph

In Figure 2 a family of curves was plotted with R2 = 200 ohms and R1 taking on the values shown. The sweep is 100V in 100 mSec, so the abscissa is equal to 1V per millisecond. If we perform a little more detailed derivation, using a value for Vbe and for the current gain we can arrive at a better formula for the current gain to be expected.

This is not a bad way to multiply CLD current, nonetheless, even though the outputs vary a bit when R1 is a small value. Looking at the trace for R1 = 8 ohms, we see that the current changes by about 40ma over the input voltage (regulation) range of about 80 volts, much less than would occur for a series resistor implementation.

But now might this affect the AC noise rejection of the circuit?

A test circuit was created as shown in Figure 3 following:


Figure 3
NPN CLD current booster test circuit


Figure 4
NPN CLD current booster test circuit graph 1

In figure 4 we see that the DC and small signal AC voltage rejection is about 14 dB. Not as good as we would like. But the input DC voltage changes are rejected by that same amount. Figure 5 following is a transient graph of the circuit:


Figure 5
NPN CLD current booster test circuit graph 2

Here we see in Figure 5 that there is a sine wave of about 308 uV peak at the output.

Now to reduce the AC output level some more, we could add a capacitor across the zener diode. Refer to Figure 6 following:


Figure 6
NPN CLD current booster test circuit 3


Here we added a 100uF across the zener diode. Figure 7 following is a transient graph of this circuit:


Figure 7
NPN CLD current booster test circuit 3 transient graph

In Figure 7 we have added an ESR to the filter capacitor. The AC peak voltage is about 250uV. An AC sweep of the circuit produces the graph shown in Figure 8 following:


Figure 8
NPN CLD current booster test circuit 3 AC sweep graph

The AC sweep of the circuit in Figure 3 shows that the AC signal rejection starts to become effective at about 14 Hz and adds additional AC rejection.

The final test circuit is shown in Figure 9 following:


Figure 9
NPN CLD current booster test circuit 4

In Figure 9 we added resistor R5 to provide a resistance to form the resistive 'tee' filter as shown in the previous article. One side of the 'tee' is the output impedance of the CLD multiplier device itself. The other side was a 100 ohm resistor, small enough to add a DC voltage drop of only about 10V, yet large enough to give C1 some resistance to react with. A transient graph of this circuit is shown in Figure 10 following:


Figure 10
NPN CLD current booster test circuit 4 transient response

In Figure 10 we see that the output AC has a transient that lasts for about 100mS. This occurs as the maximum charging current for the capacitor C1 is about 100ma.

An AC sweep of the circuit produces the graph shown in Figure 11 following:


Figure 11
NPN CLD current booster test circuit 4 AC sweep

In Figure 11 we see that there is no appreciable difference between the response of Figure 8 and that of Figure 11. From the previous CLD paper we saw that the ratio of the two resistances that 'bridged' the filter capacitor should be somewhere between 0.3 and 0.7. But here the output impedance of the current multiplier circuit is somewhat large, making the addition of a sufficiently large value for R5 drop too much DC voltage (the 400 ohm resistor drops 40v as the CLD current multiplier output is about 100 ma.)

The conclusion is that the circuit of Figure 6 is as good as we can get, essentially, save for some other modifications.

Conclusions:

A current multiplier circuit can extend the useful output current of a CLD diode, although the output DC and AC change rejection will suffer somewhat. Some additional investigation should be performed if this circuit is used in a precision application to ensure that the noise performance is adequate.

References:

  1. Central Semiconductor, SPICE models and datasheet:
    http://www.centralsemi.com/spicemodels/spicecld.aspx


Current Limiting Diodes: Part 4


Summary: Current Limiting Diodes, also called Current Regulating Diodes or Constant Current Diodes, are devices that act like a dual of a zener diode. That is, over a range of applied voltage they will exhibit a constant current characteristic. Refer to the previous articles on Current Limiting Diodes (Current Limiting Diodes parts 1 through 3.

This CONCLUDING article will discuss a model that may be used for an ideal CLD and for other purposes.

Ideal current limiter Device Model:

A putative model for a current limiter with test circuitry is shown in Figure 1 following:


Figure 1
Current Limiter Device Test circuit

The B1 device, as shown, incorporates the equation:

v = v(n1, n2)> {Vk}? {Ik} + (V(n1,n2)- {Vk})* (({Ikm} - {Ik})/({Vkm} - {Vk})): v(n1,n2)*{ik}/{Vk}

This equation creates a two segment, first quadrant, device that mimics the performance of a Current Limit Diode (CLD). The parameters passed are those items shown in 'curly brackets'.

A nested ITE expression is used to create this device. The logical function is:

IF the device current is positive and greater than Ik
THEN the device current will be Ik plus a proportionate amount equal to the amount device voltage exceeds Vk divided by the dynamic resistance of the device when regulating
ELSE the device current will be the device current divided by the knee resistance.

The knee resistance is equal to the knee voltage divided by the knee current. The dynamic resistance is equal to:

Rd = (Vkm -Vk)/(Ikm - Ik)

The parameters passed to the circuit are:

Rs = 1e-3 ohms
Ik = 20 ma
Vk = 10V
Ikm = 100V
Ikm = 24 ma
Vkm = 100
Cp = 7p

Rs is a convergence resistance and normally need not be changed. In the model
R2 and R3 are resistors added to aid convergence. The G1 current source is a VCCS that multiplies the R3 voltage by two to create the device current.

v1 source provides a zero to 100V sawtooth voltage to create the device characteristic. The ammeter is present only for test purposes.

A graph of the circuit performance is shown in Figure 2 following:


Figure 2
Current Limiter Device Test circuit graph

V2 is the voltage across the 'load' resistance of 1 ohm, hence it should and does have the same waveform as the device current.

It would be prudent to test the device circuit to ensure that it functions properly under many circumstances. Consequently, the test circuitry was altered slightly as shown in Figure 3 following:


Figure 3
Current Limiter Device Test circuit 2

In the circuit of Figure 3, v1 source is set to 20V DC, and v3, a 1V peak to peak sine wave at 100 Hz, is added. The load is now a 1N4742 diode. A graph of the circuit response is shown in Figure 4 following:


Figure 4
Current Limiter Device Test circuit 2 graph 1

The device current is the top black trace, and the zener voltage is shown in the lower red trace. This shows that the application of a 1 V peak-to-peak signal results in an output variation from 11.977 to 11.966 or 11 mv.

Now, using v2 as a 1v zero degree source for an AC sweep, the following trace results:


Figure 5
Current Limiter Device Test circuit 2 graph 2

In Figure 5 we see that the rejection of the source voltage is about 38 dB to about 200 kHz. There are some interesting interactions with the zener diode model, however it seems the model works nicely.

However, some questions need to be answered before making a subcircuit model. The model as shown is again a single quadrant model. Normally one never reverse biases the device, however, it could happen. In that event, the underlying device, which is a gate to source shorted JFET, behaves under reverse bias as a forward biased diode. But what diode characteristics are applicable to use in general, and how should one prepare a model for use that may be tailored, or should one just concentrate on the current limiting diode characteristics?

Clearly several possibilities are possible. What will be done is to insure that the device passes current in the normal current limiting direction, and in the reverse direction it is an open circuit. In that manner it may be paralleled with a diode, real or ideal, to model the reverse direction behavior if required. Now of course this may affect the current limiting characteristics if other than an ideal is used, so some care must be used.

This will require a slight modification of the model. The B1 generator equation at present is:

v = v(n1, n2)> {Vk}? {Ik} + (V(n1,n2)- {Vk})* (({Ikm} - {Ik})/({Vkm} - {Vk})) : v(n1,n2)*{ik}/{Vk}

The first test will determine that the applied voltage is positive, so the then condition is fine, but the ELSE condition will always be applied. What can be done is to change this term 'v(n1,n2)*{ik}/{Vk}' to an ITE expression of the form:

V(n1,n2)>0? V(N1,N2)*{Ik}/{Vk}: 0

Thus the new expression becomes:

v = v(n1, n2)> {Vk}? {Ik} + (V(n1,n2)- {Vk})* (({Ikm} - {Ik})/({Vkm} - {Vk})):
V(n1,n2)>0? V(N1,N2)*{Ik}/{Vk}: 0

The revised test model is shown in Figure 6 following:


Figure 6
Modified Current Limiter Device Test circuit

In Figure 6, V1 provides a voltage sawtooth from -100 to +100 volts in amplitude. The graph of this circuit is shown in Figure 7 following:


Figure 7
Modified Current Limiter Device Test circuit

In Figure7 we see that the device is an open circuit for negative applied voltages, and for positive voltage the previous model behavior is exhibited. We need to prepare a parameterized subcircuit model for this device that we will call a vCLD or variable current limiting device. Using the circuit shown in Figure 8 we can prepare such a device.


Figure 8
Final Current Limiter Device Model

Figure 8 shows the device model and the parameterized subcircuit device model with the usual CLD device symbol. In this case the part has an 'X' designator to indicate it is different than a CLD model based on a JFET.

The netlist for this circuit is as follows:

************************
* B2 Spice Subcircuit
************************
*
* Prepared by Harvey Morehouse
*
* This model may be freely copied and modified but
* is requested that the original credits to B2SPICE and
* are retained.
*
* This model will not pass a reverse current.
*
* passed parameters are:
*
* Rs - series convergence resistor
* Ik - initial current limiting value at Vk volts
* Vk - knee voltage
* Ikm - current value at Vkm
* Vkm - voltage at Ikm
* Cp - stray capacitance, typically 3-10 pf for CLD devices
*
* Pin # Pin Name
* N1 N1
* N2 N2
.Subckt vCLD N1 N2
***** main circuit
R3 7 0 10
R2 5 7 10
B1 5 0 v = v(n1, n2)> {Vk}? {Ik} + (V(n1,n2)- {Vk})* (({Ikm} - {Ik})/({Vkm} - {Vk})): V(n1,n2)>0? V(N1,N2)*{Ik}/{Vk}: 0
R4 N1 4 {{Rs}}
G1 4 N2 7 0 2
C1 N1 N2 {{Cp}}
.ends

Conclusions:

A method of making a model for a user variable CLD device was presented. This device only passes current in the forward, current limiting direction. It may be paralleled with other devices to model the reverse voltage direction behavior.

This model was based on a current source being controlled by the device current. A similar model could have been prepared based on setting the device voltage based on the current through the device. However this device works nicely.

Another method of creating this device could have been with a pwl device or the newly added pwl function, however the pwl function was not working correctly at the time of this article.