### Current Limiting Diodes (part 4)

About the writer: Harvey Morehouse is an EE contractor/consultant with many years of experience using circuit analysis programs. His primary activities are in Reliability, Safety, Testability and Circuit Analysis. He may be reached at harvey.annie@verizon.net. Simple questions regarding my articles for which I know the answer are free. Complex questions, especially where I am ignorant of the answers, are costly!!!

Summary: Current Limiting Diodes, also called Current Regulating Diodes or Constant Current Diodes, are devices that act like a dual of a zener diode. That is, over a range of applied voltage they will exhibit a constant current characteristic. Refer to the previous articles on Current Limiting Diodes (Current Limiting Diodes parts 1 through 3.

This CONCLUDING concluding article will discuss a model that may be used for an ideal CLD and for other purposes.

Ideal current limiter Device Model:

A putative model for a current limiter with test circuitry is shown in Figure 1 following:

Figure 1
Current Limiter Device Test circuit

The B1 device, as shown, incorporates the equation:

v = v(n1, n2)> {Vk}? {Ik} + (V(n1,n2)- {Vk})* (({Ikm} - {Ik})/({Vkm} - {Vk})): v(n1,n2)*{ik}/{Vk}

This equation creates a two segment, first quadrant, device that mimics the performance of a Current Limit Diode (CLD). The parameters passed are those items shown in 'curly brackets'.

A nested ITE expression is used to create this device. The logical function is:

IF the device current is positive and greater than Ik
THEN the device current will be Ik plus a proportionate amount equal to the amount device voltage exceeds Vk divided by the dynamic resistance of the device when regulating
ELSE the device current will be the device current divided by the knee resistance.

The knee resistance is equal to the knee voltage divided by the knee current. The dynamic resistance is equal to:

Rd = (Vkm -Vk)/(Ikm - Ik)

The parameters passed to the circuit are:

Rs = 1e-3 ohms
Ik = 20 ma
Vk = 10V
Ikm = 100V
Ikm = 24 ma
Vkm = 100
Cp = 7p

Rs is a convergence resistance and normally need not be changed. In the model
R2 and R3 are resistors added to aid convergence. The G1 current source is a VCCS that multiplies the R3 voltage by two to create the device current.

v1 source provides a zero to 100V sawtooth voltage to create the device characteristic. The ammeter is present only for test purposes.

A graph of the circuit performance is shown in Figure 2 following:

Figure 2
Current Limiter Device Test circuit graph

V2 is the voltage across the 'load' resistance of 1 ohm, hence it should and does have the same waveform as the device current.

It would be prudent to test the device circuit to ensure that it functions properly under many circumstances. Consequently, the test circuitry was altered slightly as shown in Figure 3 following:

Figure 3
Current Limiter Device Test circuit 2

In the circuit of Figure 3, v1 source is set to 20V DC, and v3, a 1V peak to peak sine wave at 100 Hz, is added. The load is now a 1N4742 diode. A graph of the circuit response is shown in Figure 4 following:

Figure 4
Current Limiter Device Test circuit 2 graph 1

The device current is the top black trace, and the zener voltage is shown in the lower red trace. This shows that the application of a 1 V peak-to-peak signal results in an output variation from 11.977 to 11.966 or 11 mv.

Now, using v2 as a 1v zero degree source for an AC sweep, the following trace results:

Figure 5
Current Limiter Device Test circuit 2 graph 2

In Figure 5 we see that the rejection of the source voltage is about 38 dB to about 200 kHz. There are some interesting interactions with the zener diode model, however it seems the model works nicely.

However, some questions need to be answered before making a subcircuit model. The model as shown is again a single quadrant model. Normally one never reverse biases the device, however, it could happen. In that event, the underlying device, which is a gate to source shorted JFET, behaves under reverse bias as a forward biased diode. But what diode characteristics are applicable to use in general, and how should one prepare a model for use that may be tailored, or should one just concentrate on the current limiting diode characteristics?

Clearly several possibilities are possible. What will be done is to insure that the device passes current in the normal current limiting direction, and in the reverse direction it is an open circuit. In that manner it may be paralleled with a diode, real or ideal, to model the reverse direction behavior if required. Now of course this may affect the current limiting characteristics if other than an ideal is used, so some care must be used.

This will require a slight modification of the model. The B1 generator equation at present is:

v = v(n1, n2)> {Vk}? {Ik} + (V(n1,n2)- {Vk})* (({Ikm} - {Ik})/({Vkm} - {Vk})) : v(n1,n2)*{ik}/{Vk}

The first test will determine that the applied voltage is positive, so the then condition is fine, but the ELSE condition will always be applied. What can be done is to change this term 'v(n1,n2)*{ik}/{Vk}' to an ITE expression of the form:

V(n1,n2)>0? V(N1,N2)*{Ik}/{Vk}: 0

Thus the new expression becomes:

v = v(n1, n2)> {Vk}? {Ik} + (V(n1,n2)- {Vk})* (({Ikm} - {Ik})/({Vkm} - {Vk})):
V(n1,n2)>0? V(N1,N2)*{Ik}/{Vk}: 0

The revised test model is shown in Figure 6 following:

Figure 6
Modified Current Limiter Device Test circuit

In Figure 6, V1 provides a voltage sawtooth from -100 to +100 volts in amplitude. The graph of this circuit is shown in Figure 7 following:

Figure 7
Modified Current Limiter Device Test circuit

In Figure7 we see that the device is an open circuit for negative applied voltages, and for positive voltage the previous model behavior is exhibited. We need to prepare a parameterized subcircuit model for this device that we will call a vCLD or variable current limiting device. Using the circuit shown in Figure 8 we can prepare such a device.

Figure 8
Final Current Limiter Device Model

Figure 8 shows the device model and the parameterized subcircuit device model with the usual CLD device symbol. In this case the part has an 'X' designator to indicate it is different than a CLD model based on a JFET.

The netlist for this circuit is as follows:

************************
* B2 Spice Subcircuit
************************
*
* Prepared by Harvey Morehouse
*
* This model may be freely copied and modified but
* is requested that the original credits to B2SPICE and
* are retained.
*
* This model will not pass a reverse current.
*
* passed parameters are:
*
* Rs - series convergence resistor
* Ik - initial current limiting value at Vk volts
* Vk - knee voltage
* Ikm - current value at Vkm
* Vkm - voltage at Ikm
* Cp - stray capacitance, typically 3-10 pf for CLD devices
*
* Pin # Pin Name
* N1 N1
* N2 N2
.Subckt vCLD N1 N2
***** main circuit
R3 7 0 10
R2 5 7 10
B1 5 0 v = v(n1, n2)> {Vk}? {Ik} + (V(n1,n2)- {Vk})* (({Ikm} - {Ik})/({Vkm} - {Vk})): V(n1,n2)>0? V(N1,N2)*{Ik}/{Vk}: 0
R4 N1 4 {{Rs}}
G1 4 N2 7 0 2
C1 N1 N2 {{Cp}}
.ends

Conclusions:

A method of making a model for a user variable CLD device was presented. This device only passes current in the forward, current limiting direction. It may be paralleled with other devices to model the reverse voltage direction behavior.

This model was based on a current source being controlled by the device current. A similar model could have been prepared based on setting the device voltage based on the current through the device. However this device works nicely.

Another method of creating this device could have been with a pwl device or the newly added pwl function, however the pwl function was not working correctly at the time of this article.