### Time Delay: Part 1

About the writer: Harvey Morehouse is a contractor/consultant with many years of experience using circuit analysis programs. His primary activities are in Reliability, Safety, Testability and Circuit Analysis. He may be reached at harvey.annie@verizon.net. Simple questions for which I know the answer are free. Complex questions, especially where I am ignorant of the answers, are costly!!!

Summary: A fixed time delay is often useful. One such application, a dead time generator, is useful where two switching transistors cannot be simultaneously turned on. This could be where, in a half-wave bridge type application, the turn-on on one device is delayed following the turn off of the other device. Another use is in SMPS models to delay switching transistor turn-on during intervals where switching noise could be present.

The problem is that often other variables may be changing in the course of an analysis, and using pwl devices, logical equations, or some circuit implementations might be cumbersome. In this case a delay line is used. This was suggested by Chris Basso and described in his book (Reference 1).

Time Delay:

A basic time delay circuit using a delay line is shown in Figure 1 following: Figure 1
UTD Time Delay Circuit

Figure 1 shows the basic circuit, with the default levels of the T1 model. The test generator V1 with source impedance (resistance) R2 equaling 1K is shown driving the UTD circuit consisting of T1 and R1 connected as shown. In this case, the Zo value of T1 is set to equal 1K. Figure 2 following shows a graph of the circuit. Figure 2
UTD test circuit graph #1

Figure 2 shows the applied voltage (before the source resistance) in red, the input to the UTD circuit in green, and the delayed UTD output in purple.

The time delay input is interesting. Recalling our transmission line courses, at the instant of application of a signal the transmission line presents an impedance to the source (in this case equal to 1K + 0.001 ohms) initially. Thus the input signal is halved. A waveform of current and voltage travels down the transmission line. After the delay line time delay, in this case 2 usec, it reaches the end.

However, the impedance seen by this incident wave of current is essentially infinite, and the current is reflected back as a negative value. At the same time, this causes the output voltage to rise to essentially the full voltage level of the source. After another 2 usec, the reflected current reaches the source where it cancels the original current, and presents an essentially open circuit to the source. This causes the voltage at the transmission line source to step to the input voltage. The same process happens essentially in reverse during the interval when the source returns to zero.

Figure 1 following shows two delay circuits to be used in in a half-bridge or synchronous type rectification deadtime circuit. Figure 3
NEWDT circuit

Looking carefully at Figure 3, two UDT circuit types are used to create the circuit - UTD implying a Unit Time Delay. This device consists of a transmission line and an input resistor.

Each UTD device is imbedded into an Inverted Leading Edge Detector circuit. The AND gate compares the input signal with a delayed input signal (through the UTD device). When BOTH signals are true, which will occur after the delay time programmed into the transmission line (assuming of course the input persists longer than the delay time set within the transmission line), the output will be true for as long as the undelayed signal is true.

There was an interesting problem with the circuit. Recalling from Figure 1, when there is a source impedance, one has to set the transmission characteristic impedance to this value. From Figure 2, this causes the voltage at the transmission line input to dwell at half of the input level for two time delays. Now it is possible that the input signal could be almost any level at its extremities. And, a logic inverter device might have a differing source impedance. The simplest way to handle this was to use B1 and B2 devices to buffer the input, with the B2 output device having the logical inverse output of the B1 device. Both devices have zero source impedance, and hence the stepped level at the input of the delay line does not occur. Figure 4
NEWDT circuit graph

The first delay circuit has the orange curve signal as one input. This produces the green output from the delay line. AND'ing these two signals produces the black
'Q' output.

In a similar manner, the second circuit has as its input the signal of the red trace, and the second delay line produces an output represented by the blue trace. AND'ing these two signals produces the bottommost blue trace as a 'Qbar' output.

It is clear to see that, assuming of course that positive levels turn on the output devices, that the two signals do not overlap and that there in an interval of 'TD' seconds between the turn-off of one device and the turn-on of the other.

Both of these devices are useful, and should be added to the standard library as parameterized subcircuits. The two devices, devoid of test circuitry, are shown in Figures 5 and 6 following: Figure 5
UTD circuit and suggested symbol

Again, this should be a parameterized subcircuit model, with Zo and TD passed to the device.

The NEWDT model is shown in Figure 6 following: Figure 6
NEWDT circuit and suggested symbol

The model in Figure 6 is passed the parameters shown. Some explanation is in order, however. Vlow is used to determine when the input level is high or low, causing the appropriate stimulus to be applied to the delay lines. Devices B1 and B2 always product outputs of one or zero volts. As these sources have zero output impedance, Zo = R1 = R2 = 0.001 ohms. TD is of course the time delay in seconds.

Rout is the output resistance of the AD gates, in ohms. Volow and Vohi are the excursion limits of the AND gate output signals.

The AND gates are slightly changed from those in the library to enable the output levels to be adjusted, and the output resistance chosen. A netlist of this circuit is:

***** subcircuit definitions

************************
* B2 Spice Subcircuit
************************
* Pin # Pin Name
* N1 N1
* N2 N2
* N3 N3
.Subckt and_sub N1 N2 N3

***** main circuit
B1 4 0 v= (u(v(n1)-.{VOlow}) * u(v(n2)-{VOlow}))*({VOhi} - {VOlow}) + {VOlow}
R1 4 N3 {Rout}
R2 N1 0 1G
R3 N2 0 1G

.ends

***** main circuit
T1 3 0 1 0 z0 = .001 f = 1e10 td = {TD} nl = .25
T2 10 0 9 0 z0 = .001 f = 1e10 td = {TD} nl = .25
R2 IN 3 .001
R1 13 10 .001
XU2 13 9 Qbar and_sub
B2 13 0 v = 1-u(v(N1)-{Vlow})
R5 N1 0 1G
XU1 IN 1 Q and_sub
B1 IN 0 v = u(v(N1)- {Vlow})

.end

Summary:

Using a delay line a fixed time delay circuit and a dead time generator circuit has been produced.

References:

1. Switching Mode Power Supply Cookbook, McGraw Hill, ISBN 0-07-137509-0

### Time Delay: Part 2

Summary: A fixed time delay is often useful. One such application, a dead time generator, is useful where two switching transistors cannot be simultaneously turned on. This could be where, in a half-wave bridge type application, the turn-on on one device is delayed following the turn off of the other device. Another use is in SMPS models to delay switching transistor turn-on during intervals where switching noise could be present.

The previous circuit showed a device (NEWDT) that produced non-overlapping drive outputs both referenced to ground. While this could produce control signals for switches which represented transistors, it is not usable to drive MOSFET 'N' (or 'P') devices in the high side in general, as a high side 'N' or 'P' device requires a signal which is not referenced to ground

Time Delay:

A basic time delay circuit using a delay line was prepared in the previous article, and is shown in Figure 1 following: Figure 1
UTD Time Delay Circuit

Please refer to the previous article for a description of this circuit, which will be used in the creation of the NEWDT2 device.

Figure 2 following shows two delay circuits to be used in a half-bridge or synchronous type rectification dead time circuit. (NOTE: as in the case of the NEWDT circuit, the AND gates are slightly modified to allow the setting of the high and low output levels, as well as the input offset voltage. Figure 2
NEWDT2 circuit

Each UTD device is imbedded into an Inverted Leading Edge Detector circuit. The AND gate compares the input signal with a delayed input signal (through the UTD device). When BOTH signals are true, which will occur after the delay time programmed into the transmission line (assuming of course the input persists longer than the delay time set within the transmission line), the output will be true for as long as the undelayed signal is true.

The difference in this case from the circuit of the preceding article, NEWDT, is that the high side 'N' CMOS driver is offset by a level equal to that on the input on the OFFset pin. A test circuit for this circuit is shown in Figure 3 following: Figure 3
NEWDT2 test circuit #1

In Figure 3 we added a square wave generator as a source, while the voltage at the OFFset input was set at 5V. The B3 source voltage is programmed to be, in this case,

v= u(u(v(IN)-.8) +u(v(INd)-0.8)-1.01)*(10 - .3) + .3 +v(OFFset,0)

The expression is in a general format suitable for use with B2SPICE version 4 and 5, as well as SPICE3 products in general. A graph of this test circuit produces the graph in Figure 4 following: Figure 4
NEWDT2 test circuit #1 graph

Here we see that the high side drive output is offset by 5V.

A netlist for this circuit showing the parameterized values follows:

NEWDT2 dead time device.cpr * created by Harvey C. Morehouse

*
* based on the Model created by Christophe Basso

***** subcircuit definitions

************************
* B2 Spice Subcircuit
************************
* Pin # Pin Name
* N1 N1
* N2 N2
* N3 N3
.Subckt and_sub N1 N2 N3

***** main circuit
B1 4 0 v= u(u(v(n1)- {Vlow)) +u(v(n2)- {Vlow})-1.01)*({Vohigh} - {Volow}) + {Volow}
R1 4 N3 {Rout}
R2 N1 0 1G
R3 N2 0 1G

.ends

***** main circuit
T1 3 0 INd 0 z0 = .001 f = 1e10 td = {TD} nl = .25
T2 10 0 9 0 z0 = .001 f = 1e10 td = {TD} nl = .25
R2 IN 3 .001
R1 13 10 .001
XU2 13 9 Qbar and_sub
B2 13 0 v = 1-u(v(N1)-.5)
B3 12 0 v= u(u(v(IN)- {Vlow}) +u(v(INd)- {Vlow})-1.01)*({VOhigh} - {Volow}) + {Volow} +v(OFFset,0)
R5 N1 0 1G
B1 IN 0 v = u(v(N1)-.5)
R3 12 GU {Rout}

.OPTIONS method = gear
.end

Uses for this circuit would be in a half wave bridge rectifier, but it could also be used in a SMPS switching regulator model with a high side 'N' type CMOS transistor and another 'N' type CMOS transistor in parallel with a flywheel diode - as in a Buck or a Buck-boost converter.

Summary:

A dead time generator circuit has been produced with an offset high side driver suitable for use in a half wave bridge rectifier and certain types of SMPS controller switching models.

References:

1. Switching Mode Power Supply Cookbook, McGraw Hill, ISBN 0-07-137509-0