### Current Limited Supply Device: Part 1

About the writer: Harvey Morehouse is a contractor/consultant with many years of experience using circuit analysis programs. His primary activities are in Reliability, Safety, Testability and Circuit Analysis. He may be reached at harvey.annie@verizon.net. Simple questions for which I know the answer are free. Complex questions, especially where I am ignorant of the answers, are costly!!!

Summary: When performing an analysis, voltages provided by a power supply circuit are often abstracted as perfect voltage sources. Often this is a good approximation for government work!! With well-behaved loads and often some not-so-well behaved ones, this has no major effect on the simulation. And usually one uses worst-case high and low voltage value to evaluate the effects of the supply(s) on the circuit.

Practical voltage power supplies used in a circuit have limits to the current they can provide and accept while staying in regulation. If the loading stays within those limits there is no need to do otherwise than use perfect voltage sources in most instances, however in certain cause a more detailed model is needed.

The Need for Ideal Current Limited Supply

A current limiting supply device for usage where a power supply does not, and cannot accept nor provide more than given values of current is often required. Now one of course could use a detailed power supply model, however, the usual practice is to model portions of a large model, and when the smaller portions are determined to performing within proper limits, to perform an abstraction on that circuit portion and to replace it with a simpler model. This shortens simulation time considerably.

This is done frequently, where power supply levels are represented as constant voltage sources. However, there arrive situations where this might not be realistic. Consider a SMPS buck regulator as a load to a supply. During the turn on interval, with a constant input voltage applied at time zero, the input current can surge to very large levels.

Unless the voltage is present and at the 'final' level, when the converter is 'turned-on', it may be unrealistic to use a constant supply voltage level. Now it may be permissible to do this, as a worst-case situation, but this could cause some components to be overstressed in the simulation. And some results, such as turn-on time, could be optimistic.

Now even IF the voltage is present at converter turn-on, there will still be some practical limit to the amount of current that may be drawn from the supply before it will fall out of regulation. Likewise, most supplies are sources of current. They will source current, but if the load forces current back into the power supply, the power supply voltage will rise. And even where they can sink current, as in the case where a shunt regulator circuit is present at the output of the source supply, there is some limit to the current they can accept and stay within regulation.

Now one artifice that will ease the problem somewhat, in the case where the source voltage is turned on at the same time as is an SMPS circuit load without inherent current limiting, is to 'ramp-up' the source voltage. Then, the demands of the load may be within reasonable values.

However, even in this case, there might be problems with an 'overhauling load' (where the output load returns power to the input source). And the normal currents the supply was demanded to provide by the load could be excessive at turn-on. Moreover, the SMPS controller/circuit might have an UVLO (Under Voltage Lock Out) feature, which could defeat most if not all of the input source ramping.

Now a current-mode controller for the SMPS load could alleviate this somewhat or even totally by limiting the peak source current demanded IF this were provided, but such a controller might not be used.

This was the impetus for creating this current limiting circuit, which in some regards behaves in part as a bilateral CLD device, were there such a thing.

Ideal current limiter Device Model:

In this model we will need two current limiter devices. The reasons for this will be seen shortly. First we need to create a positive current limiting device. This device will only pass current in the forward direction. Second, we need a device that will limit current in the forward direction, and pass currents in the reverse direction with no interference. Later we will see the reason for this.

These devices will be made into parameterized subcircuits for possible use in other devices, however it is not contemplated at this time that they will be used The models created will be named vclim1 and vclim2, the first being the unidirectional current device and the second, the device that limits in just one direction.

v =v(n1,4)> {If}*{Rs}? v(n1,n2) - {If}*{Rs} : v(n1,4)> 0 ? 0 : v(n1,n2)
v =v(n1,4)> {If}*{Rs}? v(n1,n2) - {If}*{Rs} : 0

The vclim device models, together with test circuitry, are shown in Figure 1 following: Figure 1
vclim models

In Figure 1, the two vclim device models are shown. vclim1 is the top circuit consisting of everything to the right of the N1 and N2 terminals, with the test circuitry to the left. Beneath is shown the vclim2 device, consisting of all to the right of the N3 and N4 terminals, with its test circuitry shown to the left

The B1 device incorporates the equation:

v =v(n1,4)> {If}*{Rs}? v(n1,n2) - {If}*{Rs} : v(n1,4)> 0 ? 0 : v(n1,n2)

What this equation does is to determine if the current is greater than If in the test. If so, a voltage, which is just enough to oppose any further current increase above, this amount is created for positive voltages and currents. Whereas, if the voltage is positive, and the current is less than If , no opposing voltage is created. But if the voltage is not positive, an opposing voltage is created that will make the device current zero.

The B2 device incorporates the simpler equation:

v =v(n1,4)> {Ir}*{Rs}? v(n1,n2) - {Ir}*{Rs} : 0

If the voltage is such that the current is greater than Ir, an opposing voltage enough to oppose any further current increase above this amount is created. But in this case, if the current is less than the Ir value, no opposing voltage is created.

Now the B1 and B2 generator outputs are divided by two with a resistive divider. The output voltage across R3 (R5) is used by the E1 (E2) generator with a gain of two, to create the opposing voltage.

The reason for the resistive divider(s) is to aid in convergence of the circuit(s) by allowing slight numerical calculation errors to occur, as the circuit cannot read the future, and predict exactly what the current would be, and present the exact voltage required to prevent it from occurring. This is similar to a feedback amplifier. With a finite amplifier gain, some error voltage has to be present.

A graph of the circuit is shown in Figure 2 following: Figure 2
vclim models graph

In Figure 1, the top two curves are associated with vclim1 and the bottom two with vclim2. It is clearly seen that the vclim1 device does not pass current in the reverse direction and limits current in the forward direction. vclim2 device also limits current in the forward direction, but there are no limits in the reverse direction. For convenience models of these devices will be prepared. The convergence resistor Rs will be common to both devices, but vclim1 will have its forward current designated as parameter If and vclim2 will have will have its forward current designated as parameter Ir, reflecting its later usage in the current limited source device.

Ideal Current Limited Supply:

The vclim1 and vclim2 devices were turned into parameterized device models for convenience. The program generated symbols were uses, as at this time it is expected that these devices will be mostly if not entirely used to create other devices.

A model for a currently limited supply using these devices is shown in Figure 3 following: Figure 3
current limited supply model

Figure 3 shows a model for a current limited supply device model with test circuitry. The test circuitry consisting of those parts outside of the box.

V2 is provided to prevent the ground device from overriding the N2 node designation, as it would do if not isolated by a zero volt source. N1 and N2 are subcircuit markers that are required when creating a part. Without V2, some internal device equations would change when the test parts are removed and the remaining current limited supply device is itself turned in to a parameterized subcircuit device.

In this circuit the source V1 is used to charge capacitor Cp through U1, the unidirectional current limiting device model. Cp has an associated series resistance that may be made arbitrarily small if desired.

The capacitor voltage (including the effects of R1, Rcser ohms, directly is connected to the load through the supply dynamic resistance R2, of dynamic resistance Rd ohms.
Rd acts on forward and reverse supply currents, which might be incorrect for the case of currents being supplied to the source (capacitor), and it could have been used within the vclim2 device model to eliminate its effects for reverse currents, however if this becomes a problem at a later date it is easily corrected.

Cp was added because the reverse current would otherwise directly change the output voltage (via the voltage across the reverse current limiter) in a larger than expected manner. In this case the current is integrated by Cp to create a rising output voltage when vclim1 is not passing current and vclim2 is.

For the forward current limiting case, a simulation was performed where:

Vs = 10V
If = Ir = 1A
Rcser = 0.05 ohms
Rd = 0.05 ohms
Vcpi = 0V
Cp = 100uFd
Rs = default = 1e-3 ohms

A graph of the circuit is shown in Figure 4 following: Figure 4
current limited supply model test #1

In Figure 1, it is seen that the source enters forward current limiting almost immediately. This is seen from the blue trace of the V1 supply current. (The V1 current is negative because it is supplying power.) At about 6.7 ms the forward current limiting stops when the vcls1 device stops supplying current to Cp, and the load, which also was being charged by the source, shows a stable voltage at the load capacitor after about 10 ms.

The green v3 trace shows the output supply voltage, and the red v4 trace shows the voltage across the load capacitor.

Now here a little flaw is shown by the model by introspection. The vclim2 device does not function correctly in the model. If there was some active shunt regulation in the load, there should be a current limiting function in parallel with Cp. Vclim1 current limit should be set to the nominal output current plus this current, and the shunt regulating current should be set to absorb load current returned by the source up to some limiting value when the vclim current goes to zero and becomes negative. Thus, vclim2 does not work correctly and should be removed, and the model becomes valid only for a source with limiting of positive source current.

Still, the model is useful for the typical power sources that do not have shunt current regulation at their output. Making this correction to the model, and changing the test load such that it will provide a negative current for some periods of time produces the circuit shown in Figure 5 following: Figure 5
current limited supply model2

In Figure 5 we have added a ammeter Am1 to enable us to clearly see the load current magnitude and sense. The load capacitor was removed, as was resistor R3. I1 was added to provide a current square wave of current from zero to 60 ma.

The nominal supply current is thus 10V/200 ohms or 50 ma. With I1, the load current will vary from 50ma to -10 ma at a frequency of 50 Hz. The graph of this circuit is shown in Figure 6 following: Figure 6
current limited supply model2 graph

In Figure 6 we can see the effect of the 10 ma of reverse current on the green v3 output voltage trace being a approximate 60 mv voltage rise. Were Cp not present the voltage rise would be much greater. During the negative current interval Cp charges. The Cp discharge time is somewhat shorter, however until the voltage decays to the nominal 10V no current is passed to the load by the source v1. The capacitor Cp alone supports the load until the output voltage decays to 10V.

Now the output voltage rise is dependent on the frequency of the load changes, the value of Cp and of course the magnitude of the reverse current. There is another complication, which is that a real DC-DC converter could have its output voltage soar if the load was 'dropped' as the output inductor could continue charging Cp through a filter inductor (charged to the average load current before the load was lessened). Whereas, if the inductor current decayed sufficiently, the recovery could be hampered by the time it took the inductor current to be re-established.

Adding an inductor seems to be a worthwhile addition, so, let us add this to the model and investigate what happens.

The circuit is shown in Figure 6 following: Figure 7
current limited supply model3

Here we have added a fixed, linear inductor to the model, with nothing else changed from the previous circuit. Parameters Ls (100uH) and inductor initial current Ilsi (0ma) were added. The start-up behavior is shown in Figure 8 following: Figure 8
current limited supply model3 graph 1

In Figure 8 we notice that in the green v3 output trace the output voltage reaches a peak of about 11.9v, and then decays to 10V. This 19% overshoot may or may not be realistic. Meanwhile, the source voltage is clamped to 2A for about 560us, and then it decreases rapidly. When the output voltage v3 settles to about 10V at about 4ms, there is some oscillation in the supply current and the output current, due to the LC ringing.

To see the effects of the current variations, the circuit was again graphed, but with the sweep starting now at 14ms, when the transients have settled own. This is shown if Figure 9 following: Figure 9
current limited supply model3 graph 2

In Figure 9, it is seen from the black trace of I(Am1) that the load current supplied by the source goes both negative and positive. When the I1 current step goes to zero, the output capacitor Co starts supplying the load. When the v3 output voltage decays to 10 volts, the source again starts providing current through vclim1, but the abrupt start of current causes the LC portion of the circuit to be shock-excited and to start ringing. The actual effect on the output voltage is small however.

Examination of the circuit shown that the resonant frequency should be:

F = 1/( 2*Pi()*L*Cp)1/2

or 1.59KHz. An quick examination of the curves reveals this is the case.

This model is certainly suitable to model most 'positive' current providing sources, and also some sources without active shunt regulation at the output, It will be converted into a circuit model Voilim, denoting a current source limiting device. At a later time a model may be created for a sourcing and sinking supply device. Of course there is nothing preventing a user creating their own model to do this.

Practically, it must be observed that a supply would often be supplying other loads than those shown when examining a portion of a system, and that load capacitance would also likely be present, mitigating the effects of what might be a localized current sourcing and sinking load. However IF this source current loading overall can occur some not-so-nice effects may occur.

As a last step, a behavioral model was created for the current limited supply3, and a device created. A test circuit for this model was used along with the test circuit in Figure 7, as shown in Figure 10 following. Figure 10
current limited supply model3 test 2

Here we have a final test for our parameterized device model (shown as U2), comparing its results to that of the model on which it was based. The results are shown in Figure 11 following: Figure 11
current limited supply model3 test 2 graph

In Figure 11 it can be seen that the v3 (original circuit) and v4(device model) test circuit results are identical.

The following is the netlist for the voilim device:

************************
* B2 Spice Subcircuit
************************
*
* Created by Harvey Morehouse
*
* This circuit models a supply level with a limited
* output source current and no shunt limiting.
*
* Passed parameters are:
* Rs - convergence resistance
* Rd - dynamic output resistance
* If - max fwd current
* Cp - source output capacitance
* Rcser - series resistance of Cp
* Vcpi - capacitor initial voltage
* Ls - inductance
* Ilsi - initial inductor current
*
* Normally Rs is not altered.
*
* This circuit may be freely used and altered however credit
* should be given as above.
*
* Pin # Pin Name
* N2 N2
* N1 N1
.Subckt Voilim N2 N1
***** subcircuit definitions
************************
* b2 spice subcircuit
************************
* pin # pin name
* n1 n1
* n2 n2
.subckt vclim1 n1 n2
***** main circuit
vam1 4 6 0
r3 7 0 10
r2 5 7 10
b1 5 0 v =v(n1,4)> 2.000000000000e+000 * 1.000000000000e-003 ? v(n1,n2) - 2.000000000000e+000 * 1.000000000000e-003 : v(n1,4)> 0 ? 0 : v(n1,n2)
r4 n1 4 1.000000000000e-003
e1 6 n2 7 0 2
.ends
***** main circuit
R2 12 N1 {Rd}
R1 12 6 {Rcser}
C1 6 N2 {Cp} ic = {Vcpi}
XU1 3 11 vclim1
V1 3 N2 {Vs}
L1 11 12 {Ls} ic = {Ilsi}
.ends

Conclusions:

A model was created for a non-ideal voltage source reflecting a positive output current capability. (It may be inverted to create a negative voltage source.) This model will limit output current to a specified value (save for what might be provided by the source output capacitance in addition to the source limit.

It is not suitable for use with supplies that provide current sinking capabilities. While it is as approximation of a typical SMPS supply, it is intermediate between an ideal voltage source used as a model and an SMPS supply model.

### Current Limited Supply Device: Part2

Summary: When performing an analysis, voltages provided by a power supply circuit are often abstracted as perfect voltage sources. Often this is a good approximation for government work!! With well-behaved loads and often some not-so-well behaved ones, this has no major effect on the simulation. And usually one uses worst-case high and low voltage values to evaluate the effects of the supply(s) on the circuit.

Practical voltage power supplies used in a circuit have limits to the current they can provide and accept while staying in regulation. If the loading stays within those limits there is no need to do other than to use perfect voltage sources in most instances, however in certain cases a more detailed model is needed.

The Need for Ideal Current Limited Supply Device - Revisited

A current limiting supply device for usage where a power supply can and does accept both positive and negative values of current loading, and/or where very fast current load changes can occur is sometimes required.

One such instance is when current mode logic is used. In that event very abrupt and often large current changes can occur. The problem is that the output voltage, while regulated, is usually provided by an inductor charging an output capacitor. This limits the ability of the supply to respond to fast increases in loading.

When the load decreases rapidly, the inductor will continue to charge the capacitor until its current decreases to the proper average current level of the load. Now the power supply will respond and lower or even stop charging the output capacitor as required, but this is not instantaneous.

And if the load current reverses direction, the current will also charge the output capacitor increasing the output voltage.

To cover those conditions, and/or to provide for better regulation for even just fast load changes, a shunt regulator is often provided. Such a regulator is usually biased to somewhat more than the maximum load current change that is expected. Properly designed it will respond to load changes more rapidly than could occur for a supply that can only source current.

Ideal Shunt regulator:

In order to create a model for the Ideal Current Limited Supply 2, first we will create an idealized shunt limiter circuit. This device will attempt to keep the voltage across its terminals constant by increasing (or decreasing its current from a normal value) up to preset limits. It will not decrease its current below zero, and it may have some practical limit to the current it can pass.

There are many possible considerations. In some cases the output may be protected by a 'crowbar' circuit that places a low resistance across the output capacitor if the voltage becomes excessive. In that event often the supply must be un-powered to recover, assuming that it can sustain the load without damage. Sometimes the supply may sense a shorted load, and prevent operation until the short is removed. In other instances a fuse or breaker may be opened. These considerations will not be covered in this article. Certainly if a detailed examination of a supply is required, a detailed model should be used. Here we wish to approximate the operation in a reasonable manner.

Ideal Current Limited Supply 2:

A tentative model for a shunt limiter with a test circuit is shown in Figure 1 following: Figure 1
Shunt limiter test circuit

In Figure 1, the test circuitry is everything to the left of the N1 and N2 terminals, while the remainder of the circuitry to the right is that of the shunt limiter. V3 is a zero volt source preventing the ground from causing the N2 terminal to be renamed.

B1 and B2 sources implement the controlling equations for the G1 current source. The B1 device equation is:

v = if(V(n1,n2) > {Vs}, ((V(n1,n2) - {Vs})/{Rs}) + {Is}/2 , ( if(V(n1,n2) > 0, ((V(n1,n2) - {Vs})/{Rs}) + {Is}/2, 0)) )

This equation is really rather simple, consisting of two ITE expressions, one nested within the other. The first (outer ITE expression) determines if the device terminal voltage is greater than Vs, the nominal output voltage. If so, a voltage (representing a current value) is created. The value is equal to half of the shunt current maximum value plus an amount proportional to that which the terminal voltage exceeds the Vs value.

Whereas, if the voltage does not exceed Vs, the value is Is/2 less a proportionate amount less that the voltage is less than Vs. The THEN condition establishes this condition. It is in a nested ITE loop, which determines if the device voltage is greater than zero. If not, the current is limited to zero.

There is no positive limit to the current, however it is convenient to examine the B1 output in the B2 device to establish this limit. The expression for the B2 generator is:

v = if(v(5) > {Is}, {Is}, if(v(5) < 0, 0, v(5) ) )

Is is the current limiting maximum value. If the current commanded is greater than Is, it is limited to Is. Whereas, if it is less than zero, it is limited to zero. Otherwise, the v(5) value from the B1 generator is used.

G1 is a voltage controlled current source, with a gain of unity. Am1 and Am2 are ammeters used for test only.

It is assumed that half of the maximum current is the nominal current at Vs. Thus with Is equal to 2 amps, at Vs it would draw 1 amp, and allow for fast changes of 1 amp increasing or decreasing current to occur with little effect.

Now current limiters are a little tricky, and some thought often is required to understand what is happening, particularly when they are imbedded within more complex circuits.
V1 was set at 1 volt, 1 kHz, and Vs at 5v. The graph of this circuit is shown in Figure 2 following: Figure 2
Shunt limiter test circuit graph 1

In Figure 2 we see that the output voltage, red trace v2 persists at 5v. The green trace of the current through R5 is also constant. The effect of the varying sine voltage from V4, which would otherwise cause R5 current to change, is absorbed by the shunt regulator circuit, which is nominally drawing 1A.

Well, now let us change v4 amplitude to 1.5 amps, and observe the graph of Figure 3, which follows: Figure 3
Shunt limiter test circuit graph 2

In Figure 3 we have a more interesting set of circumstances. The shunt regulator can only pass currents between zero and 2A, and it falls out of regulation when these limits are exceeded. The little bumps of voltage on the red output voltage, and the green load current values occur when the shunt regulator reaches the limits.

Now there are many interesting things one can experiment with in this circuit, but we will forego that pleasure and create a parameterized subcircuit for this device. The circuit is shown in Figure 4 following: Figure 4
Shunt limiter circuit and model

The netlist for this device is:

************************
* B2 Spice Subcircuit
************************
*
* Created by Harvey Morehouse
*
* Shunt regulator
*
* Vs is the shunt regulator voltage
* Is is the max shunt regulator current
*
* at vs across its terminals Is/2 current is passes
*
* This circuit may be freely copied and used
* however it is requested that B2SPICE and myself are credited.
*
* Positive terminal = N1
* Negative terminal = N2
*
* Pin # Pin Name
* N1 N1
* N2 N2
.Subckt ishuntr N1 N2
***** main circuit
B1 5 0 v = if(V(n1,n2) > {Vs}, ((V(n1,n2) - {Vs})/{Rs}) + {Is}/2 , ( if(V(n1,n2) > 0, ((V(n1,n2) - {Vs})/{Rs}) + {Is}/2, 0)) )
R4 N1 4 {Rs}
G1 4 N2 11 0 1
R6 11 0 10
B2 11 0 v = if(v(5) > {Is}, {Is}, if(v(5) < 0, 0, v(5) ) )
.ends

Having made a parameterized subcircuit model for this device, we can proceed to use it with the current limited circuit device model developed in the previous article. The original model, together with she shunt regulator device added and test circuitry, is shown in Figure 5 following: Figure 5
Full limited supply test circuit

For the first test the values used were:

Vs = 10V
If = Is = 2A
Rcser = 0.05 ohms
Rd = 0.05 ohms
Vcpi = 0V
Cp = 100uFd
Rs = default = 1e-3 ohms
L1 = 100uH
Ilsi = 0

The graph of this circuit is shown in Figure 6 following: Figure 6
Full limited supply test circuit graph 1

The load current change due to I1 is positive and negative 0.5A. At the nominal 10V output the shunt regulator is able to handle these variations. There is a slight variation in the output voltage due to the dynamic output resistance. This may be seen in Figure 7 following: Figure 7
Full limited supply test circuit graph 2

In Figure 7 we see that the voltage change at the output (neglecting the spikes) is about 50 mv. This figures, as a one-ampere change in output current multiplied by 50 milliohms is 50 mv.

Now, changing I1 to vary from -1 to +1 amps, with all else unchanged, we arrive at the grapy of Figure 8. Figure 8
Full limited supply test circuit graph 3

In Figure 8 it is seen that the output voltage change (neglecting the spikes) is double that of the previous test. The spikes are caused by the inductor, When loading is removed, the inductor current slowly decreases while the shunt regulator takes up the change in current until the inductor current decreases.

But when loading is added, the inductor current cannot increase immediately, there are several things happening. Looking at the curve of I(v1) - and remembering it is shown as negative when it is delivering power to the load - during the removal of load it ramps down but the addition of loading causes a rapid increase in current. This increases the inductor voltage, which is in series with V1 and in opposition to it.

There are many more tests that could be performed under different conditions of loading. This could include comparison of this circuit performance under loading with the output of the previous circuit, too many to be included here. These will be left for the reader to perform. Consequently the circuit shown in Figure 9 following will be converted into a parameterized subcircuit model named voirilim, denoting a voltage source whose output and reverse current capability is limited, Figure 9
Full limited supply circuit

In Figure 9 the circuitry to be turned into a parameterized subcircuit is shown together with the symbology for the device, shown as U2. The netlist for this device is:

************************
* B2 Spice Subcircuit
************************
*
* created by harvey morehouse
*
* this circuit may be freely copied and used
* however it is requested that b2spice and myself are credited.
*
* Voltage source with current limiting and current sinking
*
* Parameters passed:
*
* Vs - source voltage
* If - forward max current
* Is - shunt regulator max current
* Rcser - shunt capacitor series R
* Rd - output dynamic resistance
* Vcpi - filter capacitor initial voltage
* Cp - capacitance of filter capacitor
* Rs - convergence resistor
* L1 filter inductance
* Ilsi - inductor initial current
*
* Pin # Pin Name
* N2 N2
* N1 N1
.Subckt voirilim N2 N1
***** subcircuit definitions
************************
* b2 spice subcircuit
************************
*
* created by Harvey Morehouse
*
* shunt regulator
*
* this circuit may be freely copied and used
* however it is requested that b2spice and myself are credited.
*
* vs is the shunt regulator voltage
* is is the max shunt regulator current
*
* at vs across its terminals is/2 current is passed
*
*
* positive terminal = n1
* negative terminal = n2
*
* pin # pin name
* n1 n1
* n2 n2
.subckt ishuntr n1 n2
***** main circuit
b1 5 0 v = if(v(n1,n2) > 1.000000000000e+001 , ((v(n1,n2) - 1.000000000000e+001 )/ 1.000000000000e-003 ) + 2.000000000000e+000 /2 , ( if(v(n1,n2) > 0, ((v(n1,n2) - 1.000000000000e+001 )/ 1.000000000000e-003 ) + 2.000000000000e+000/2, 0)) )
r4 n1 4 1.000000000000e-003
g1 4 n2 11 0 1
r6 11 0 10
b2 11 0 v = if(v(5) > 2.000000000000e+000 , 2.000000000000e+000, if(v(5) < 0, 0, v(5) ) )
.ends
************************
* b2 spice subcircuit
************************
* pin # pin name
* n1 n1
* n2 n2
.subckt vclim1 n1 n2
***** main circuit
vam1 4 6 0
r3 7 0 10
r2 5 7 10
b1 5 0 v =v(n1,4)> 2.000000000000e+000 * 1.000000000000e-003 ? v(n1,n2) - 2.000000000000e+000 * 1.000000000000e-003 : v(n1,4)> 0 ? 0 : v(n1,n2)
r4 n1 4 1.000000000000e-003
e1 6 n2 7 0 2
.ends
***** main circuit
VAm1 12 4 0
R2 4 N1 {Rd}
R1 12 6 {Rcser}
C1 6 N2 {Cp} ic = {Vcpi}
XU1 3 11 vclim1
V1 3 N2 {Vs}
L1 11 12 {Ls} ic = {Ilsi}
XU4 12 N2 ishuntr
.ends

One little quirk is present in the netlist. When parameterized subcircuits are used within a parameterized subcircuit, and the netlist is created for the overall circuit, the netlist does not show the parameterized values in the sub-parameterized parts. This is a nuisance, but the lower level parts are indeed parameterized.

The test circuit for this part is shown in Figure 10 following: Figure 10
Full limited supply circuit

The circuit of Figure 10 was used to compare the performance of the parameterized part U2 to that of the circuit used to create it. A graph of the performance is shown in Figure 11 following: Figure 11
Full limited supply circuit rest

In Figure 11 it is evident that the v3 and v4 outputs are identical. Additional inspection (not shown) confirms this is so.

Conclusions:

A model was created for a non-ideal voltage source reflecting current sourcing and sinking capability. (It may be inverted to create a negative voltage source.)

While it is as approximation of a typical SMPS supply, it is intermediate between an ideal voltage source used as a model and an SMPS supply model. It does not simulate instantly, but it does respond faster than would a more complete SMPS model and is suitable for use with other circuits to examine the effects of current sourcing and sinking when the loads are not well behaved.