Leading Edge Blanking (LEB)

About the writer: Harvey Morehouse is a contractor/consultant with many years of experience using circuit analysis programs. His primary activities are in Reliability, Safety, Testability and Circuit Analysis. He may be reached at harvey.annie@verizon.net. Simple questions regarding my articles for which I know the answer are free. Complex questions, especially where I am ignorant of the answers, are costly!!!

Summary: Leading edge blankers are often used in SMPS controller chips, particularly when current mode control is used and where the switch current is monitored. This is because the transistor switch current may show spikes of current when the switch is turned on, disturbing the modulation control. Also, typically where an SMPS is modeled with switch turn-on at the start of a conduction cycle, the error voltage is small and noise can be present.

It is not easy to model noise conducted or induced into a circuit accurately, but the delay of conduction could be important to the circuit (and model) performance. And in a push-pull application, or with a two transistor synchronous switch application, it could be important to ensure that the two transistors are not simultaneously turned on. A behavorial model of a Leading Edge Blanking circuit will be created to model this action.

In an averaged model this is not a major consideration, but in a switching model it could affect performance by slightly delaying the start of a conduction cycle, or by preventing overlap of drive pulses.

A Leading Edge Blanking circuit will be created that can model this behavior.

LEB device model:

The LEB device is based on the LED2/TED2 circuits which use a delay line implementation. Please refer to the LED2/TED2 article. The basic LED2-TED2 circuits are shown in Figure 1 following:

Figure 1
LED2-TED2 device test circuit

A transient graph of the circuit is shown in Figure 2 following:

Figure 2
LED2-TED2 device test circuit graph

A slight change in output is required to obtain a LEB output. If the un-delayed circuit input less the leading edge is output we have the desired, leading edge blanked signal. This is clearly the 'AND' of the original input and the transmission line delayed output.

Now here we arise at a little problem. If we are going to use LOGICAL equation operators, some care is needed. Were the input and outputs logical levels, TRUE and FALSE levels (1.00…0000 and 0.00…000 levels, there would be no problem. However, to allow this circuit to operate with somewhat arbitrary input voltage levels, the logic gate level amplitudes of the signals must be preserved at the outputs.

Choices of logical operators (the '$' logical operator) uses logical levels, whereas the '&' logical gate operator converts the signals from logical gate option values to logical values and then back to logical gate values, that could be different than the actual levels desired.

So, to avoid this we will use comparison operators, as was done with the LED2/TED2 circuit, to direct the output level to be a parameterized high or low logic level. The resultant (test) circuit is shown in Figure 3 following:

Figure 3
TEB device test circuit

A transient graph of the circuit output is shown in Figure 4 following:

Figure 4
TEB device test circuit graph

In Figure 4 the middle signal is the un-delayed input. The topmost signal is the transmission line delayed signal, and the bottom signal is the leading edge blanked output signal.

The parameters passed to the circuit are shown in Figure 5 following:

Figure 5
TEB device model user defined parameters

Figure 5 shows the user defined parameters for the circuit. Because it has not been turned into a parameterized subcircuit device yet, it does NOT include the transmission line parameters, which are shown in Figure 6 following:

Figure 6
Transmission line user defined parameters

In Figure 6, the ONLY entry that needs to be changed is the value of td, the value of the leading edge blanking in seconds.

If and when this device is turned into a parameterized subcircuit device, all of the parameters of Figures 5 and 6 will be presented for user entry as parameterized subcircuits in B2 SPICETM as is 'flat', with subcircuits used in the device model passing their values up to the highest level.

Now, and interesting question is how does one get trailing edge blanking, were one to wish this? Well, you cannot, at least is the manner performed here unless the signal were periodic of a known length. It is not possible to know when the pulse is supposed to end, and shorten it, without some additional information.


A TEB circuit has been created that produces a leading edge blanked signal.