Boolean Algebraic & Logical Expressions in B2.Spice
By Harvey Morehouse
Contents:
 Logical Functions: Part 1
 Logical Functions: Part 2
 Logical Functions: Part 3
 Logical Functions: Part 4
 Logic and Ideal Diodes
 Bilateral Diode Clamp
 HalfWave Bridge
 FullWave Bridge
 Erroramp2
 OTA1
 NO Smooth Switches : Part 1
 NO Smooth Switches: Part 2
 B2.Spice A/D Gates
 B2.Spice A/D Logical Expressions: Part 1
 B2.Spice A/D Logical Expressions: Part 2
 B2.Spice A/D Logical Expressions: Part 3
Logical Functions: Part 1
About the writer: Harvey Morehouse is a contractor/consultant with many years of experience using circuit analysis programs. His primary activities are in Reliability, Safety, Testability and Circuit Analysis. He may be reached at harvey.annie@verizon.net. Simple questions for which I know the answer are free. Complex questions, especially where I am ignorant of the answers, are costly!!!
Summary: Although not as convenient as in some SPICE implementations, it is possible to implement Boolean algebraic expressions in B2 Spice as part of the nonlinear voltage or current source or otherwise. Some methods of doing this are presented here.
Nonlinear source implementation:
There is a unit step function which may be used to implement an 'IF…THEN…' function. There is unfortunately an ambiguity in this function, similar to the indeterminate results one gets with digital logic. This can be overcome with a little work.
Specifically, the ustep function returns a logical 'ONE' if its argument is greater than zero, logic 'ZERO' if the argument is less than zero, and an indeterminate if the argument is equal to zero. Thus, one could add an expression such as the following to a nonlinear source:
V = u(v(2,0))
This would produce ALMOST what we expect. However, the source must be bipolar (negative and positive going) otherwise the result will ALWAYS be a logic 'ONE'. However, if we are interested in a logical comparison of the signal to a level, we could write the expression as:
V = u(v(2,0)K)
This produces (almost) a greater than function. If the parameter v(2,0) is unipolar, and it is desired to return a logic ZERO when v(2,0) is equal to zero, then K becomes an arbitrarily small number. This value may then be used as a multiplier to provide an IF..Then function (almost). Assume that v(2,0) is unipolar. Then K = K1 if we wish to get a logic ONE when it is (essentially) greater than zero, where K1 is arbitrarily small.
We then may get an AND function by multiplying together two ustep functions, as in:
V = u(v(2,0)*v(5,4))
Similarly summing the signals produces an OR function. A negate is produced by reversing the nodes of a source, or by use of a '' operator.
A simple test circuit was produced to examine these functions. The circuit is shown in Figure 1 following:
Figure 1
Logic circuits (first pass)
The netlist for this test circuit is:
Circuit2 ************************ * B2 Spice ************************ * B2 Spice default format (same as Berkeley Spice 3F format) ***** main circuit V1 LA 0 DC 0 PULSE( .0001 1 0 1u 1u 1m 2m) V2 LB 0 DC 0 PULSE( .00001 1 .51m 1u 1u 1m 2m) R1 LA 0 1K R2 LB 0 1K B1 AND 0 v=(u(v(LA))*u(v(LB)))*3 B2 OR 0 v=u((u(v(LA))+u(v(LB))).000001)*3 B3 AnotB 0 v=u((u(v(LA))*u(v(LB))).0001)*3 B4 notAnotB 0 v=u((u(v(LA))+u(v(LB)).000001))*3 .OPTIONS gmin = 1E12 reltol = 1E4 itl1 = 500 itl4 = 500 + rshunt = 1G .TRAN 10u 10m 0 1u uic .IC .END 
One can examine the outputs of this circuit by performing a transient analysis.
Figure 2
Transient test of Circuit 1
It should be noted that these signals are 'well behaved', that is to say, they do not dwell at a zero level when the constant is part of the expression or not. Note that for the sources B2, B3 and B4 a unit step of the inner step functions is performed. The reason for this is that those functions WILL produce an indeterminate logic state. Consequently, as this logic state is between a ZERO and a ONE logic state, it can be cleared by subtracting a K1 value and performing a unit step on that output. (Because the logic functions are 'wellbehaved' this step was not needed for the 'AND', however in general it would be.)
So, in using the nonlinear source for logical functions, construct the ustep functions using a constant in all cases, either as a comparison or to convert a unipolar signal to a bipolar one.
Combine the ustep functions together as products or sums. Perform another ustep of these functions with a value of K1 sufficient to make the inner ustep function bipolar.
Then, multiply this function by the desired 'THEN' value.
Now if one needs an 'ELSE' condition, one may negate the 'IF' expression, multiply this by the 'OR' result, and then sum the two products together (making sure that the required constant values and ustep of the inner ustep terms is performed. It is not 'clean', but it will work.
One may wish to use several nonlinear sources as intermediate elements to keep one's sanity and to aid debugging.
Logical Switch Implementation:
A second approach is to model the logic functions with switches. This has the advantage that the logical ambiguity is NOT present at the switch outputs, although it is at the switch inputs. However the switch toggle levels and hysteresis is controllable in the switch elements. The following shows an IF..THEN implantation of switches.
Figure 3
Switch Logic implementation
In this circuit, the nonlinear generator output is present at R1 if SA AND SB, OR SC AND SD ARE ACTUATED. With levels A, B, C, and D controlling the respective switches, the logic is:
IF ((A AND NOTB) OR (C AND D)) THEN V(B1) ELSE ZERO
The circuit is so self evident no netlist is required. In this case, if a control voltage were unipolar, then the trip level would be set to some arbitrarily low level. The switches should have a very low 'ON' resistance compared to R1, with a very large 'OFF' resistance compared to R1 as well.
An
ELSE condition can be arrived at several ways, but one is shown in
Figure 4 following:
Figure 4
IF ..Then..Else circuit
In the above, a voltage across R1 is asserted to control S1 and S2. S1 and S2 have identical conditions. The logic then becomes, IF ((A OR NOTB) AND C AND NOTD) THEN B1 ELSE B2.
Logical gate implementation:
It should be self evident how to construct such logic with gates, comparators and so on. However, the use of other than Xspice devices should be avoided wherever possible UNLESS one is modeling a device where such items as delay times, rise and fall times and so on are required.
Looking Ahead:
It has been established that one CAN implement logical functions into nonlinear sources or by switches or gates implement such functions. So what?
One MAJOR use for this is in the modeling of Switching Mode Power Supplies (SMPS). Simple, fast computing models and techniques have been created which allow the effects of a variable duty cycle control to occur, while enabling an operating point to be established. Within a given switch cycle, one state occurs while the switching transistor in 'ON' and another while it is off. And, there is a third state which can be modeled; however this shall not be described here. The point is, that these conditions can best be modeled by logical equations rather than by circuitry with many state changes occurring rapidly, all the while performing extensive analog computations.
Rapid, yet realistic modeling of SMPS control IC's as well as the switching elements that allows stability determinations to be made is what logical equation capability brings to the table. While this is NOT a total replacement for detailed device modeling in some instances, it can produce results and insights into SMPS operation impossible in any other manner.
References:
No specific references are given, as the ideas, though not original to me, have been discussed and used for several years. One could not however discuss SMPS modeling without mentioning the pioneering work of Middlebrook, Ridley, Sandler, Bello and many others. Not mentioning any of them would be a crime, yet mentioning all of them and their contributions would be a major paper in itself. SMPS analysts are in debt to dozens of pioneers.
Logical Functions: Part 2
Summary: In previous article I showed how to create logical expressions. While largely correct, there were some misleading statements and errors in the article. In order to correct these items, this short correction is provided.
Nonlinear Source 'u' element:
Contrary to what was written and implied, THERE IS NO AMBIGUITY IN THE OUTPUT OF THE U ELEMENT. For a given f(v,Z,t), the output of a u(f(v,Z,t)) operation will return an output which is unity when the argument is greater than zero, and zero otherwise. This may be seen from examination of the test circuit of part 1 of this article.
There may be a seeming ambiguity in some logical operations using 'u' expressions. If two or more 'u' expressions are summed, the output is NOT a logical OR of the two 'u' expressions but an arithmetic sum of the values of the 'u' expressions. Consequently, given functions f(a), f(b), ….f(z) where it is desired to get an output when any of these functions are greater than zero, it must be recognized that in this case one might get 26 different levels from the sum of the 'u' values for each expression.. Each nonzero level could represent different combinations of individual 'u' expressions. Consequently, in every case where 'u' expressions are summed to get a logical 'OR' output, an outer 'u' of this sum must be performed in order to get a unity multiplier for some output value.
Where
'u' expressions are multiplied, any single zero 'u' expression over
an interval will 'blank' the overall product during that interval,
and the overall product will be unity or zero, consequently a product
of individual 'u' expressions (where these inner products are themselves
corrected if they are the result sums of 'u' expressions) will be
correct.
An Aside:
This correction became apparent when I was looking into the possibility of incorporating majority logic expressions into a simulation. Basically majority logic assigns differing logical 'weights' to differing gate inputs. When a majority 'weight' is present the gate will switch.
This was implemented by a simple sum of 'u' expressions which each were multiplied the appropriate 'weight'. The sum of these expressions was compared to a majority value in an outer 'u' sum of the individual terms.
Logical Functions: Part 3
Summary: In previous article entitled Boolean Algebraic expressions  Corrections I made some corrections to the first article which were in error.. While largely correct, there were some misleading statements and errors in the article. In order to correct these items, this short corrected correction is provided.
Nonlinear Source 'u' element:
Contrary to what was written and implied, THERE IS AMBIGUITY IN THE OUTPUT OF THE u operator. For a given f(v,Z,t), the output of a u(f(v,Z,t)) operation will return an output which is unity when the argument is greater than zero, and zero when the argument is less than zero. When the argument is zero, it is treated somewhat like an xSPICE logic element. That is to say, it becomes indeterminate, and like the xSPICE logic elements, returns an intermediate value.
The returned value is halfway between zero and one or 0.5, similar to that of the xspice element which returns a value midway between the values set for the Xspice high and low output values.
The respective values are found in version 5 through the SIMULATIONS/SPICE SIMULATIONS/MIXED MODE drop down selection sequence through the variables:
bb_daOutLow = 0 bb_daOutHigh = 5 bb_daOutX = 2.5 bb_adInLow = .5 bb_adInHigh = 4.5
In the Xspice logic elements, if the input is less than bb_adInLow = .5 it is interpreted as a logic low input, whereas if the input is greater than bb_adInHigh = 4.5 it is interpreted as a logic high level. Between these levels the input is treated as an indeterminate value, resulting in an output equal to (bb_daOutLow = 0 bb_daOutHigh = 5) /2 or 2.5 volts.
Now
for the 'u' operator, the output variations are zero and one, hence
the indeterminate output value = 0.5. Apparently there is a value
for an argument ever so slightly greater than zero which will cause
the 'u' function to return a logic one, and another ever so slightly
less than zero which causes the function to return a logic zero.
Consequently, if one were to use a generator to produce an output
which pulsed between zero and some value, and to use voltage as an
argument for a 'u' function, the output would vary between 0.5 and
1.0 (after an initial transient depending on whether the node was
set to a level at the start of a simulation or not.)
Many of my models using these functions had/have operands that were/are real values, and bipolar in nature. These would only present an indeterminate output level rarely if ever, as the likelihood of a real variable being exactly zero for any length of time is slight. The problems would arise in using those digital models for digital simulations with input signal values that varied between zero (or some small positive level) to a higher level.
Generally I tested for these cases but not always. I made an occasional error in testing these models by being lazy and using sine wave inputs in many cases. I usually included a threshold value for these devices in any event, save for comparisons between real levels. To verify this problem, the model in Figure 1 was created:
Figure 1a
Ustep test circuit
For this first test, the expression for the B1 generator is:
v = u(v(N1))
and for B2 it is:
v = u(0)
A graph of this circuit is shown in Figure 2a following:
Figure 2a
Ustep test circuit1 graph1
Here we see that N2 presents an output that varies between one and 0.5V (after the initial time zero)  whereas, the zero argument presents a constant 0.5V output. Let us now modify B1 to be:
v = u(v(N1) 1)
and B2 to be:
v = u(v(N1) .5)
The graph becomes as shown in Figure 3a following:
Figure 3a
Ustep test circuit1 graph2
Here we see that with the test of the input being at the upper limit for B1, the N2 curve now varies between unity and 0.5, instead of between 0.5 and 1.0V. Interesting. This might be useful sooner or later. The curve for N3, with a test value of 0.5, produces the desired result. Let us do one more test, changing the input voltage v1 to vary between 0.3 and 3.3V. B1 and B2 will be unchanged. The graph for these conditions is in Figure 4a following:
Figure
4a
Ustep test circuit1 graph3
Here we see that the curves behave as expected. Not shown is an zoomed in trace of the rise and fall times, for there is where we might expect to see problems if a zero argument were present.
Not shown are several traces where the input has been applied to an RC filter to slow down the transitions. The traces give no indication of problems with a 0.5 unexpected output level.
The conclusions are, that whenever operating with a unipolar type output there must be a test for the variable(s) in the argument being greater than some intermediate threshold level between the minimum and maximum input levels where switching is expected to occur.
Now inasmuch as there were some questions regarding the ustep function, it seems reasonable (for version 5.15+ which has logical equation capabilities) whether this will result in similar problems for an IF … THEN … ELSE … OR an ITE expression. The test circuit will be the same as that in Figure 1a, save that the B1 expression will be:
v = if (v(n1),1,0)
and the B2 expression will be the equivalent, or:
v = v(n1)? 1: 0
The intent is to determine if a signal with equivalent Boolean logic 1 and logic 0 voltage levels will be properly resolved by an ITE expression. The graph is shown in Figure 5a following:
Figure 5a
Ustep test circuit1 graph4
As may be seen, the ITE expression does recognize voltage levels as being equivalent to their boolean logic levels. The next question, is that if the input is offset from zero, what will happen? In Figure 6a following, the v1 generator has been changed to switch from 0.3 to 1.0 volts.
Figure 6a
Ustep test circuit1 graph5
Here we see that the same ambiguity seems to be present in an ITE expression as in the ustep function. The help file notation for the ustep function (the 'u' operator) is:
Bxx <N+> <N> [I=<expr>] [v=<expr>]
e.g.
B1 1 2 v = I(vin) + 3* I(v2)
B2 2 0 I = v(i1) + 3* v(2) + 5 * v(3) ^2Arbitrary sources use an equation to describe their behavior. One and only one of I=<expr> and V=<expr> must be given.
For the first example, this is a currentcontrolled voltage source. The v on the left side of the equation indicates that it is a voltage source. I(vin) is the current through a voltage source named vin.
In the second example, the source is a voltagecontrolled current source. V(2) represents the voltage at node 2, and v(i1) represents the voltage across a current source named i1.
The following functions are defined for real variables:
Abs, acos, acosh, asin, asinh, atan, atanh, cos, cosh, exp, ln, log, sin, sinh, sqrt, tan.The function "u" is the unit step and "uramp" is the integral of the unit step. The unit step is one if its argument is greater than zero and zero if its argument is less than zero.
The ramp function (uramp) is 0 for argument values less than zero and equal to the argument for argument values greater than zero.
The following operators are defined:
+, , *, /, ^, and unary.
The help file confirms the ambiguity for the ustep and uramp functions. Now for version 5, the preceding test as well as the version 5.1.6 release notes confirm that, within an ITE expression, the test condition must be the result of a logical expression (properly formed of course) OR equivalent to the 1/0 results of a logical expression.
There may be a seeming ambiguity in some logical operations using 'u' expressions. If two or more 'u' expressions are summed, the output is NOT a logical OR of the two 'u' expressions but an arithmetic sum of the output values of the 'u' expressions. Consequently, given functions f(a), f(b), ….f(z) where it is desired to get an output when any of these functions are greater than zero (or some threshold), it must be recognized that in this case one might get 26 different levels from the sum of the 'u' values for each expression.. Each nonzero level could represent different combinations of individual 'u' expressions. Consequently, in every case where 'u' expressions are summed to get a logical 'OR' output, an outer 'u' of this sum must be performed in order to get a unity multiplier for some output value.
Where 'u' expressions are multiplied, any single zero 'u' expression over an interval will 'blank' the overall product during that interval, and the overall product will be unity or zero, consequently a product of individual 'u' expressions (where these inner products are themselves corrected if they are the result sums of 'u' expressions) will be correct.
An Aside:
This corrected correction became apparent when. I was doing some writing for a project that hopefully will be finished at year's end.
The project involved using virtually all of the devices in the resources section, and in the process I noted some real errors aside from minor typographical errors, for which I blush. Several of the posted articles will have corrections shortly.
Logical Functions: Part 4
Summary: In previous articles I showed how to create logical expressions. Here is another way.
Nonlinear Source 'u' element:
According to the definition of the uramp function, and I quote, ""uramp" is the integral of the unit step. The unit step is one if its argument is greater than zero and zero if its argument is less than zero. The ramp function (uramp) is 0 for argument values less than zero and equal to the argument for argument values greater than zero.
Despite the misleading title, implying an integral, the uramp function returns the value of the argument when it is greater than zero. Thus, in some cases, where the 'test' is to return the value of the test when it is greater than zero, the uramp function can save some typing, and resultant errors. In other words, where an expression is to be logically,
If f(a)>0 then f(a), then one can use a nonlinear source with the voltage or current as applicable v=uramp(f(a)).
The following circuit illustrates this:
Figure 1
uramp function test circuit
The netlist for the test circuit is:
uramptest.ckt .TRAN
10u 5m 0 1u uic 
The resultant output is shown in Figure 2 following:
Figure 2
uramp function test output
Although not clear from the picture, the input at N4 overlaps the
output at N2.
I was misled by the 'ramp' part of the uramp name, actually intending to use it for another purpose; however, the intended purpose can be attained in other manners. Notice several other things. Besides being useful for logic expressions, this also functions as an ideal diode with no voltage drop.
It pays to muck around with the library functions!!!!
Logic and Ideal Diodes
Summary: In the previous article of this series I showed how to create logical expressions using the uramp function. I alluded to their use in ideal/perfect perfect diode models, without going into details. I have had several inquiries from persons who could not see how to do this. To preclude more emails and have me typing much of the same information several times, I have decided to prepare an implementation of an ideal diode and a perfect diode, and describe how an ideal zener (or breakdown) diode could be created. This paper shows how to do these things.
The goal here, however, is also to (hopefully) illustrate how, by application of fundamental engineering circuit concepts, useful devices and functions may be modeled in B2SPICE and in any SPICE3 implementation. This is done by showing some of the steps and methods I use to create models using logical equations.
Perfect Diode and Ideal Diode:
In line with previous definitions, a 'perfect' diode is one whose forward voltage drop is zero volts (or essentially so), and its current in the reverse direction, when the device has an impressed positive voltage from cathode to anode is essentially zero. It has no reverse breakdown voltage, no junction capacitance, storage time effects nor other parasitics. Its resistance in the conducting region is essentially zero.
An 'ideal' diode, on the other, hand, has a nonzero forward voltage drop where conduction begins when it is forward biased at greater than this level, as well as a breakdown voltage level where conduction occurs in the 'reverse' direction when it is reverse biased. In both cases, once the conduction level is reached, essentially no additional incremental voltage drop (due to resistance or other effects) occurs. Again, no junction capacitance, storage time effects nor other parasitics are present, but these effects could be added using additional external circuit elements.
Nonlinear Source 'uramp' element:
The preceding article in this series describes the 'uramp' function in some detail, and will not be repeated other than the definition:
According to the definition of the uramp function, and I quote, "uramp" is the integral of the unit step. The unit step is one if its argument is greater than zero and zero if its argument is less than zero. The ramp function (uramp) is 0 for argument values less than zero and equal to the argument for argument values greater than zero. Despite the misleading title, implying an integral, the uramp function returns the value of the argument when it is greater than zero. 
Infinite Impedance:
An infinite impedance (or infinite incremental impedance) condition between two nodes need not occur due to the presence of an impedance whose magnitude is unbounded (or essentially so), although it could. An infinite impedance, in effect, can occur between two nodes over a region where no current flows in response to an externally applied voltage to those nodes. This can occur if there is a voltage internal to the branch which is equal to, and in the opposite sense to, the externally applied voltage. The voltages cancel, and no current flows under those conditions.
Zero Impedance:
A zero impedance (or zero incremental impedance) state exists (under those conditions) wherein the voltage across two nodes is unchanging in response to externally applied current increment through those two nodes. This could occur when the impedance between two nodes is zero, or essentially so, but also where the current(s) incident to a node is (are) exactly matched by a current generator shunting the incident current(s) directly from one node to the other.
Ideal Diode Model:
The perfect diode model must have the following characteristics:
1. It is a twoport device (at least external to the model/subcircuit for the device).
2. When the externally applied voltage from Cathode to Anode terminals is negative, essentially no internal current must flow (subject of course to numerical error limit considerations).
3. When condition 2. is not met, the device current (and voltage) must be determined by the external circuitry, the device behaving as a short circuit (subject of course to the same numerical error limit considerations).
Using an internal opposing voltage source, one can construct a model and a test circuit for the first pass at an ideal diode as shown in Figure 1 following:
Figure 1
Ideal Diode Test circuit
A netlist for the circuit follows:
Circuit1 ************************ * B2 Spice ************************ * B2 Spice default format (same as Berkeley Spice 3F format) ***** main circuit V1 N2 0 DC 0 SIN( 0 2 10k 0 0) R1 N2 N1 1k VAm1 3 0 0 B1 5 N1 v = abs(v(n1,0))  uramp(v(n1,0)) R2 5 3 1e12 .OPTIONS gmin = 1E12 reltol = 1E4 itl1 = 500 itl4 = 500 + itl6 = 500 method = gear rshunt = 1G .TRAN 10u .14m 0 1u uic .IC .END 
Performing a transient analysis on the circuit produces the results in Figure 2. The results are as expected, with the simulated ideal diode consisting of the 'B1' and 'R2' elements, having its anode at node 'N1" and its cathode at node '3'.
Figure 2
Ideal Diode test circuit
The operation of the diode circuit is straightforward. The applied voltage is opposed by the 'B1' voltage generator. The voltage of the 'B1' generator is the resultant of two levels. The first part is the absolute value of the voltage from node 'N1' to ground. The second is the uramp value of the voltage from node 'N1' to ground. The uramp value is the value of the 'N1' voltage when it is greater than zero.
Thus, during the halfsinusoid interval when the applied voltage is (or would be) positive, the voltage is unopposed. The equivalent diode 'conducts' with an 'ON' resistance equal to that of R2. During the second, negative half of the rectified sinusoid, the voltage generator 'B1' causes the voltage at 'N1' to be opposed by an essentially equal level, resulting in no appreciable current flow. This is of course an open circuit.
Note that the currents indicated by the ammeter and by the 'B1' source value are 180 degrees out of phase. This is caused by the sense of the 'B1' generator in the circuit. For a voltage source, within that source, 'positive' conventional current flows from negative to positive levels. So far so good, however the sense of the 'B1' generator is negative when it is (for all essential purposes) nonzero. This causes the 'B1' current to seem to be wrong. However as this will be external to the diode model/subcircuit it is of no consequence.
This ideal diode could be added to the library as a device, perhaps as a symbol of a normal diode with a letter 'I' beside it to denote it as an ideal diode. This is left as an exercise for the reader.
This device can be associated with series resistance, parallel resistance and or capacitance as needed to make it somewhat less ideal and ease simulation difficulties at the transition points from conduction to nonconduction and the converse.
Perfect Diode Model:
The perfect diode model would seem to be very similar to that of the ideal diode. The differences are that it should exhibit a forward voltage drop VF when it conducts with an essentially zero incremental resistance state, and when reverse biased with a sufficiently large voltage, it will conduct at a voltage VR with an essentially zero incremental resistance state. At first glance, it would appear that one could use one ideal diode with a fixed voltage source of VF in series opposition to the forward voltage, together with an antiparallel ideal diode with a fixed voltage source of VR in series with it in its 'forward' direction. The first diode would produce the 'ON' voltage drop of VF when its net applied voltage, VinVF was greater than zero. In the reverse direction, the antiparallel diode would conduct when the overall diode voltage was less than VR.
But, it does not work. The forward characteristics can be simulated by adding a fixed voltage in series with an ideal diode, as can the reverse characteristics by a single antiparallel diode with an associated VR. But combining the two will not work. A schematic of this failed attempt to create a (partial) perfect diode in that manner is shown in Figure 3 following.
Figure 3
Perfect diode fwd conduction element
The netlist for this circuit is as follows:
Circuit1 ************************ * B2 Spice ************************ * B2 Spice default format (same as Berkeley Spice 3F format) ***** subcircuit definitions ************************ * B2 Spice Subcircuit ************************ * Pin # Pin Name * N1 N1 * N2 N2 .Subckt idiode N1 N2 ***** main circuit B1 5 N1 v = abs(v(n1,n2))  uramp(v(n1,n2)) R2 5 N2 1e12 .ends ***** main circuit V1 N2 0 DC 0 SIN( 0 2 10k 0 0) R1 N2 3 1k VF 3 4 DC .7 XD1 4 0 idiode .OPTIONS gmin = 1E12 reltol = 1E4 itl1 = 500 itl4 = 500 + itl6 = 500 method = gear rshunt = 1G .TRAN 10u .14m 0 1u uic .IC .END 
Device D1 is a subcircuit representation of the ideal diode. VF is the forward drop of the simulated perfect diode, set at 0.7V. This illustrates the forward voltage conduction portion of the perfect diode and it works as expected. Figure 4 shows the graph of this circuit, with the forward current through the device as the current through voltage source VF.
Figure 4
Forward Conduction of perfect diode
So far, so good. The reader can verify that the breakdown characteristics can be modeled by a reversed D1 and VF (becoming VR). The problem comes when one tries to parallel these items. The circuit, as shown in Figure 5, does not work properly.
Figure 5
(FAILED) perfect diode model
The circuit will not converge. Why not?
There are TWO reasons for this circuit failure. The first is due to the mixing of essentially ideal branches 350 and 360. The second is due to the improper modeling of the perfect diode itself.
Considering the first error, it must be remembered that IF a circuit element passes no current, either it has no net voltage impressed, or it has an essentially infinite impedance. In this case, when diode D1 is NOT forward biased, and the antiparallel diode is NOT forward biased (the overall perfect diode is not conducting), the voltage at node 3 cannot be determined. It cannot simultaneously be both VIN  VF, and VIN +VR or any combination thereof, as D1 and D2 are essentially open circuited.
Considering the second error, the model we assumed without thought, was wrong. There are THREE states of interest for the perfect diode. The ideal diode has only two states. The three states for the perfect diode are as follows:
State 1: When the perfect diode has an impressed voltage greater than VF, from cathode to anode, it enters a state wherein its terminal voltage is equal to VF from cathode to anode, and the current through the device is (essentially) bounded only by external circuit elements
State 2: When the perfect diode has an impressed voltage less than VR, from cathode to anode, it enters a state wherein its terminal voltage is equal to VR from cathode to anode, and the current through the device is (essentially) bounded only by external circuit elements
State 3: When the perfect diode has an impressed voltage less than VF but greater than VR, its terminal voltage shall be that of the impressed voltage (the current is essentially zero)
Another way of looking at the error is that, in the 'B' element equations, the 'scope' of the VF and VR elements, whether added directly to the 'B' element equations or explicitly added as a series generator component, may be universal across all of the states. When using logical expressions we must be careful to ensure that all of the device states are limited properly in scope.
Logically, we need to implement a voltage generator 'B' element expression which has the following effect:
Regions

Condition

Device
Voltage

I

VIN > VF

Vd
= VF

II

not(VIN > VF) and not(VIN < VR)

Vd
= VIN

III

VIN < VR

Vd
= VR

There was a specific reason for writing the region II conditions as shown. Remember that the 'u' function returns a unity value when its argument is GREATER than zero. As mentioned in a previous article, the logical inverse of this condition is a function with a value of unity when its argument is EQUAL TO or LESS THAN zero. Practically speaking, in many cases one could merely invert the original argument to arrive at this, however it is easier to visualize and always correct to create a logical inverse function. Recalling what was previously discussed, if a function exists f(v,I,z,t) such that for v = u(f(v,I,z,t)), v = 1 when the function is greater than zero. Using this level as a 'logical' voltage, its 'logical' inverse is v = 1 u(f(v,I,z,t)), which is unity when the 'u' argument is NOT greater than zero.
The expression for the 'B' generator could then be expressed as:
V = u(v(n1,0)VF)*VF +
(1  u(VRv(n1,0)))* (1 u(v(n1,0)VF))*v(n1,0) +
u(VRv(n1,0))*VR
The first line is the region 1 condition. If v(n1,0), the input voltage, is greater than VF, the device is conducting with a voltage drop of VF from anode to cathode.
The second line is the region 2 condition. In this case if the input level is NOT more negative than VR (the breakdown voltage is specified as a positive level) AND simultaneously, VIN is NOT more positive than VF (the input level is less than VF) THEN the voltage is equal to v(n1,0), the input voltage. The device is essentially nonconducting in this region.
The third line is the region 3 condition. If the input voltage is more negative than VR (making the 'u' function argument positive), then the terminal voltage is equal to VR. The device is conducting in the reverse, breakdown region with a voltage drop of VR from anode to cathode..
A test circuit incorporating this 3 region model with some modification is shown in Figure 6 following: The difference in this modified test circuit is that the three regions are separately modeled with individual generators for each region, and no modifying voltage terms for the three regions. The purpose of this test circuit is to ensure that the each individual modifier covers the appropriate region, and sum of all three of the modifiers is unity, showing that all regions are accounted for in the three terms. VIN is set to 10 VAC, VF is set to 2 volts (to accentuate the conduction region) and VR is set to 8 volts.
Figure 6
Perfect diode region test circuit
The netlist for this circuit is as follows:
Circuit1 ************************ * B2 Spice ************************ * B2 Spice default format (same as Berkeley Spice 3F format) ***** main circuit V1 N2 0 DC 0 SIN( 0 10 10k 0 0) R1 N2 N1 1k B3 N5 0 V = u(8v(n1,0)) B1 N3 0 V = u(v(n1,0)2) R2 N1 0 1e12 B2 N4 0 V = (1  u(8v(n1,0)))* (1 u(v(n1,0)2)) B4 N6 0 v=v(n3) + v(n4) + v(n5) .OPTIONS gmin = 1E12 reltol = 1E4 itl1 = 500 itl4 = 500 + itl6 = 500 method = gear rshunt = 1G .TRAN 10u .14m 0 1u uic .IC .END 
In this circuit generator B1 (voltage v(n3)) produces the multiplier for the VF term, region 1, B3 (voltage v(n5)) produces the multiplier for the VR term, region 3, and generator B2 (voltage v(n4)) produces the multiplier for the v(n1,0) term, region 2. B4 is used as a test, summing the voltages from the B1 through B3 generators. B4 should always produce a unity output after the simulation is started, showing that all regions are covered, and that there are no gaps in coverage, and also that there is no overlap (the sum never exceeds unity).
The graph of the output is shown in Figure 7 following.
Figure 7
Perfect diode region test circuit graph
It is difficult to see the details clearly in Figure 7, however, creating the circuit and running the simulation shows that the results are as desired.
The next step is to modify the circuit of Figure 6 slightly to add the multiplier coefficients, and to place generator B4 (in series with a very small resistor, which is required). Also, the large resistor is deleted. This is performed in the schematic of Figure 8 following. Note again that VF is set to 2v, and VR to 8v, with VIN being a 10V peak sine wave.
Figure 8
Preliminary Perfect Diode Test circuit
The netlist for the circuit in Figure 7 is as follows:
Circuit1 ************************ * B2 Spice ************************ * B2 Spice default format (same as Berkeley Spice 3F format) ***** main circuit V1 N2 0 DC 0 SIN( 0 10 10k 0 0) R1 N2 N1 1k B3 N5 6 V = u(8v(n1,0))*8 B1 N3 6 V = u(v(n1,0)2)*2 B2 N4 6 V = (1  u(8v(n1,0)))* (1 u(v(n1,0)2)) *v(n1,0) B4 N1 6 v=v(n3) + v(n4) + v(n5) R2 0 6 1e12 .OPTIONS gmin = 1E12 reltol = 1E4 itl1 = 500 itl4 = 500 + itl6 = 500 method = gear rshunt = 1G .TRAN 10u .14m 0 1u uic .IC .END 
A transient analysis graph of the output is as shown in Figure 9 following:
Figure 9
Preliminary Perfect Diode Test circuit graph
The output may seem a little strange at first glance, but some thought shows that it is indeed correct. During the positive half cycle of applied voltage, when the voltage applied is greater than the selected VF of 2V, current will flow. The peak current will be 8mA. The voltage across this perfect diode model will then be 2V.
During the negative half cycle of the applied voltage, when the voltage is less than 8V, the selected value of VB being 8V, current will flow in the opposite sense to that of the forward bias condition. In this case, it will be 2mA peak.
During the interval when the applied voltage level is NOT greater than VF, and simultaneously NOT less than VB, the perfect diode model will have a voltage equal to and opposing the input voltage, creating an essentially open circuit to that voltage.
The graph SEEMS to show a linear change of voltage across the diode model during this interval, however, by comparing the input voltage to the voltage across the diode model one can see that they are indeed equal, hence no current is flowing. Actually, there is some slight error due to the program using a Gmin value of conductance across each element, as well as computational rounding of values and numerical precision of the analysis, however, for almost all practical purposes with realistic external impedances it is indeed ideal. It certainly is better than any contrived ideal or perfect modeling using standard SPICE diodes.
Before we continue, it is useful to experiment with this model to cover several other cases. If one wished to create a bilateral breakdown diode, say of 5V, one could set VF and VB to 5V or some other desired value to create such a device. One could create a breakdown diode at a level of +5V by setting VF to this level (and setting VR to some large value. Alternately one could set the breakdown voltage VB to 5V, while setting VF to some arbitrarily large value.
Another interesting element one could make is a programmable reference or breakdown diode. Eventually we will create a parameterized subcircuit model for this device, and VR and VF will be passed values. These values could be variable in value, such that the conduction characteristics could dynamically controlled.
Note that VR and VF could be zero values.
The last step in testing the model is to merge the three condition generators into a single generator. This is shown in Figure 10 following:
Figure 10
Final perfect diode test mode
The netlist for this final test circuit is as follows:
Circuit1 ************************ * B2 Spice ************************ * B2 Spice default format (same as Berkeley Spice 3F format) ***** main circuit V1 N2 0 DC 0 SIN( 0 10 10k 0 0) R1 N2 N1 1k B4 N1 6 v= u(v(n1,0)2)*2 + (1  u(8v(n1,0)))* (1 u(v(n1,0)2)) *v(n1,0)+ u(8v(n1,0))*8 R2 0 6 1e10 .OPTIONS gmin = 1E12 reltol = 1E4 itl1 = 500 itl4 = 500 + itl6 = 500 method = gear rshunt = 1G .TRAN 10u .14m 0 1u uic .IC .END 
The graph for this test circuit is shown in Figure 11 following:
Figure 11
Perfect diode final test circuit graph
The graph results are as expected, with no surprises. Examination of the graph will show that the N2 voltage tracks the input voltage in the nonconduction region, despite the seemingly linear nature of the N2 voltage. The circuit is now ready to be converted into a parameterized subcircuit, using passed values of VF and VR. A schematic of such a circuit is shown in Figure 12 following:
Figure 12
Perfect Diode final model schematic
The netlist for the model for Figure 12 is shown in the following:
Circuit1 ************************ * B2 Spice ************************ * B2 Spice default format (same as Berkeley Spice 3F format) ***** main circuit B1 N1 6 v= u(v(n1,n2)VF)*VF + (1  u(VRv(n1,n2)))* (1 u(v(n1,n2)VF)) *v(n1,0)+ u(VRv(n1,n2))*VR R1 N2 6 1e10 .OPTIONS gmin = 1E12 reltol = 1E4 itl1 = 500 itl4 = 500 + itl6 = 500 method = gear rshunt = 1G .TRAN 10u .14m 0 1u uic .IC .END 
Using this netlist one can create a parameterized subcircuit for this model. It is expected that the folks at B2SPICE will see fit to add this part to their library, for consistency of use of this device if needed.
Conclusion:
An ideal diode model has been easily created using logical equations. This model is perfectly usable, however, caution must be used if two such devices are conducted in antiparallel. It is usable however as a single level diode clamp circuit, or as a single rectifier diode.
A perfect diode model has also been created using logical equations. This also is usable singly, however as in the ideal diode model, care must be used if two such devices are to be connected in antiparallel.
Using the techniques shown herein one can create defining equations for such a bilateral clamp circuit and create a suitable model by defining the performance over its regions of operation and creating a logical expression which
The
perfect diode model could be used with the proper values of VR and
VF to create a bilateral clamp circuit, or a breakdown diode, or a
bilateral breakdown diode.
If one needs a bilateral clamp circuit, it is better to use a perfect
diode model where one polarity clamp level might be VF and the opposite
polarity clamp level VR. These can be passed values.
Why do we need such devices? Do we need such devices? Often in modeling a circuit we wish to simplify the analysis by neglecting parasitics, or, we wish to create a behavioral model for a device, subsystem or system. A behavioral model is a simpler circuit which performs in the manner of the real circuit without all the complexity. These devices can be used in this manner.
Logical
equations CAN be implemented in B2SPICE (and other SPICE3 compatible
products) to model many such interesting devices and circuits. The
techniques to do this have never, to my knowledge, been described
and published anywhere, before my articles.
Bilateral Diode Clamp
Summary: In previous articles of this series I showed how to create logical expressions and implement ideal and perfect diode models. These models do not fully work in all cases when two such diodes are connected essentially in parallel or in antiparallel. I have decided to prepare an implementation of an antiparallel diode pair suitable for use as a bilateral clamp circuit. This is a natural extension of the work in the previous articles. The model is semiideal in that it incorporates a forward diode drop (which could be zero), but there is no breakdown voltage for these diodes.
Bilateral Diode Clamp:
A diode clamp circuit consists of two antiparallel diodes, with one diode anode connected to the other diode cathode. Normally in this configuration this is the point at which the signal will be limited in its positive and negative excursions. At the 'dangling' cathode the negative limit level will be connected, and at the 'dangling' cathode the positive limit level will be presented. The signal at the diode junction will then be limited to no more than VF volts more positive, or VF volts less negative than the respective clamp levels.
The respective diode currents will be limited by whatever impedance is presented at the respective clamp level and by that of the signal being clamped.
Why would one wish to create such a circuit? Often when one uses a behavioral model for a device (particularly IC realizations) or when one creates such a model, the linear range of the device is unlimited. But in the 'real' circuit the voltage excursions cannot exceed the power supply 'rails'. Now 'real' diode devices may be used in these models, however modifying a diode to produce one with a very small voltage drop is problematic, and it also leaves one with a realization which has many other associated elements and parasites to consider.
If the clamp level is unilateral, that is to say there is but one clamp level, the previously ideal diode or perfect model will work nicely. But these models do not work well in a bilateral clamp configuration (nor in a bridge configuration as well. It is to create a behavioral model, suitable for use with other behavioral elements to create circuits that will simulate rapidly, that this device is intended.
Clamp
Circuit Model:
A test circuit illustrating this is shown in Figure 1 following.
Figure 1
Bilateral Clamp Test Circuit
One of the diodes (D1) is represented by nonlinear source B1 and resistor R1, and the second diode (D2) by nonlinear source B2 and resistor R2. The topology of the clamp circuit is shown below the main circuit. Voltage source B1 and resistor R1 represent equivalent diode D1, while source B2 and R2 represent equivalent diode D2.
Before attempting to add the equations for B1 and B2 it is useful to first evaluate the possible conditions for the conduction and noncondition for diodes D1 and D2. To make the model most useful all possible conditions will be explored. Note: Despite the sense of B2 being the same as B1, its underlying equations will make its equivalent diode inversely connected to that of B1.
In the most general case, voltages V1 and V2 could be such as to cause both diodes to conduct at the same time. Moreover, conduction of D1 would NOT preclude D2 conduction, the converse also being true. While diodes D1 and D2 would not normally simultaneously conduct, there is nothing to prevent this in usage of this new device.
Using a similar 'IF THEN ELSE' construct for the generators B1 and B2, as used for the half wave diode bridge implementation, with conduction being the default condition, the logical voltage expression for source B1 becomes:
v = IF NOT (v(n1,n3) > VF ) THEN v(n1,n3) ELSE VF
In the syntax of available B2SPICE (SPICE3) logical expression capabilities, the equation for D1 becomes:
v = 1 + u( 1  u(v(n1,n3)  1))*(v(n1,n3) 1)
The logical expression for diode D2 is a little trickier, because the diode D2 conducts when v(n3) is less than v(n2) by VF volts. The conduction condition is (v(n3)  VF)< v(n2).
For diode D2, the logical function to be implemented is:
IF NOT ((v(n2) + VF )) > v(n3) THEN (v(n2)  v(n3)) else VF
In the syntax of available B2SPICE (SPICE3) logical expression capabilities, the equation for D2 becomes:
v = 1 + ( 1  u(v(n3,n2)  1))*( v(n3,n2) + 1)
Placing these expressions into the circuit of Figure 1, it becomes as shown in Figure 2 following (with the removal of the diodes shown as D1 and D2).
Clamp Diode Test1 Circuit
Figure 2
The netlist for this circuit is:
half wave bridge1.ckt
************************
* B2 Spice
************************
* B2 Spice default format (same as Berkeley Spice 3F format)
***** main circuit
V1 N1 0 DC 5
R1 13 N3 1e3
V2 N2 0 DC 5
R6 N3 8 1K
B1 N1 13 v = 1 + u( 1  u(v(n1)  1  v(n3)))*(v(n1)  v(n3) 1)
V3 8 0 DC 0 SIN( 0 10 1k 0 0)
B2 N2 9 v = 1 + ( 1  u(v(n3)  1 v(n2)))*(v(n2)  v(n3) + 1)
R2 9 N3 1e3
.OPTIONS gmin = 1E12 reltol = 1E3 abstol = 1pa vntol = 1uv
+ itl1 = 500 itl4 = 500 method = gear rshunt = 1G
.TRAN 10u 2m 0 1u
.IC
.END
There are no real surprises in the graph of the circuit, shown in Figure 3 following:
Diode Clamp Test1 graph
Figure 3
The sinusoidal source v3 is clamped at N3 to a level between 6 and +6 volts. VF was set a 1v for this test. If VF were set to 0v, the clamp voltage would be almost exactly plus and minus 5v, with the small error of a 1milli ohm resistance.
It is expected that the model of the clamp circuit will be added to the B2SPICE library as a circuit element.
Conclusions:
Using the
B2SPICE (or any other full SPICE3 implementation) capabilities of creating
logical functions, a nearly perfect clamp circuit may me modeled.
HalfWave Bridge
Summary: In previous articles of this series I showed how to create logical expressions and implement ideal and perfect diode models. These models do not fully work in all cases when two such diodes are connected essentially in parallel or in antiparallel. I have decided to prepare an implementation of a semi ideal half wave bridge which does not have these limitations. This is a natural extension of the work in the previous articles. I call this model semiideal in that it incorporates a forward diode drop (which could be zero), but there is no breakdown voltage for these diodes.
Half Wave Bridge:
A half wave bridge circuit consists of two diodes. First we will develop a 'positive' implementation first, wherein the two diodes are connected at their anodes (the nominal output) and each diode cathode is separately connected to some driving voltage source circuitry. Normally these connections would be the extremities of a pushpull transformer winding, with the transformer centertap grounded. The connected anodes are themselves normally connected to a load circuit.
'Positive' Bridge realization:
A test circuit illustrating this is shown in Figure 1 following.
Figure 1
Diode Bridge test circuit
One of the diodes (D1) is represented by nonlinear source B1 and resistor R1, and the second diode (D2) by nonlinear source B2 and resistor R2.
Before attempting to add the equations for B1 and B2 it is useful to first determine the different regions of operation of this circuit, which will drive their realization.
Region 1: Voltage V(n1) > V(n2) AND (V(n1)  VF) > V(n3)  (D1 conducts) 
Region2 : Voltage V(n2) > V(n1) AND (V(n2)  VF) > V(n3)  (D2 conducts) 
Region3 : Voltage V(n1) = V(n2) AND (V(n1)  VF) > V(n3)  (D1 and D2 conduct) 
Region 4: Voltage (V(n1)  VF) < V(n3) AND (V(n2)  VF) < V(n3)  (no diode conducts) 
The following table shows the diode voltages under these conditions:
Region 
D1 voltage 
D2 voltage 
1 
VF 
V(n2)  V(n3) 
2 
V(n1)V(n3) 
VF 
3 
VF 
VF 
4 
V(n1)V(n3) 
V(n2)V(n3) 
Note that WERE we to add breakdown voltage conditions to the diodes, there would be several more regions to consider. Specifically, that for regions 1 and 2 an additional condition of the nonconducting diode COULD be that it is in a breakdown region, and for region 4, three conditions could be added where one or both diodes could be in a breakdown condition. This would add 5 regions to the table of operations. And were the diodes to have different breakdown voltages, more conditions could arise.
These conditions are NOT added, however, as first, the purpose of the model is to add a SIMPLIFIED behavioral model of a half wave bridge. Second, breakdown generally will not (or should not) occur in a well designed/specified bridge under normal operating conditions. If for some reason this condition is important, it is suggested that 'real' diodes be used to construct a bridge either initially or later in the modeling and analysis to examine those conditions. (Of course the reader can add those conditions to the model if desired. This is left as an exercise for the reader.)
One COULD add the restriction that the magnitude of V(n1) was never equal to the magnitude of V(n2), removing condition 3, but for generality and also for illustration purposes this will not be done.
Given the preceding conditions, we can now create the equations for each diode. In doing so, to simplify the model slightly, we shall now implement the function in an IF THEN ELSE manner. Thus for diode D1, the voltage across it will be v(n1)  v(n3), the 'ELSE' CONDITION or 'nonconducting state, unless the conduction conditions are met,..
The conduction conditions are that v(n1) VF >v(n3) AND {v(n1)>v(n2) OR v(n1)=v(n2)}. The most interesting part is the equality condition. Remembering that the 'u' function is a 'greater than' test, its realization is a little tricky. The logical inverse of a 'greater than' condition is an 'equal to or less than' condition, not the desired 'equal to condition'. However, with a little manipulation it can be achieved.
Consider voltages 'a' and 'b'. If a> b, u(ab) = 1, whereas it is zero if a = b. Then its logical inverse, (1  u(a  b)) is zero if they are nonequal. If it is unity, a is equal to b, or a is less than b. The same is true for u(b  a). Thus, for the function (1u(a  b)) * (1u(b  a)) the only way the product can be true is if a = b, as a cannot be less than b simultaneously with b being less than a. As the terms are multiplied, the value must be zero or unity.
The logical AND of two conditions is their product.
u(v(n1)VF  v(n3)) * (1u(a  b)) * (1u(b  a))
The logical OR function is found by operating on the sum of two conditions, Consider f(a) and f(b). The OR is (almost) found by arithmetic addition. Thus, f(a) + f(b) will be greater than zero IF either f(a) or f(b) is greater than zero, however both could be true. Thus the desired function is of the form u(f(a) +f(b)), which will return a unity value if either or both are true. Note that f(a) and f(b) are logical expressions.
The ELSE result is the diode voltage if the preceding equation is not met. If the conditions are met, a multiplier of the above equation must produce the diode on voltage as a resultant. Thus, the voltage generator equation for diode D1 becomes:
V = v(n1)  v(n3) + u(v(n1)VF  v(n3)) * u(u(v(n1) v(n3)) + (1u(v(n1)  v(n2))) * (1u(v(n2)  v(n1))))* (v(n1) + v(n3) + VF)
In a similar manner, the equation for diode D2 becomes:
V = v(n2)  v(n3) + u(v(n2)VF  v(n3)) * u(u(v(n2) v(n3)) + (1u(v(n1)  v(n2))) * (1u(v(n2)  v(n1))))* (v(n2) + v(n3) + VF)
The equations are realizable enough, however, the function COULD be implemented in a somewhat 'complementary' fashion. E.G., one could implement the controlled voltage source as one where the diode was conducting unless the conditions for nonconduction were met. It is worth investigating to determine if an alternate implementation offers any simplification, but with far less explanatory verbiage.
In this case, the diode (D1) is conducting at a voltage equal to VF unless (v(n2) > v(n1) AND ( NOT (v(n1) VF > v(n3)) whereas the D1 voltage will be equal to v(n1)  v(n3). The voltage expression for the D1 model B1 source becomes:
V = VF +u(u(v(n2)  v(n1)) + ( 1  u(v(n1)  VF v(n3))))*(v(n1)  v(n3)  VF)
The similar expression for diode D2 is:
V = VF +u(u(v(n1)  v(n2)) + ( 1  u(v(n2)  VF v(n3))))*(v(n2)  v(n3)  VF)
In the D1 equation the nominal voltage is VF. However, if v(n2) > v(n1) diode D2 may be conducting, but D1 is not. Also, if NOT (v(n1)  VF > v(n3)) diode D1 is not conducting. This eliminates the cumbersome '=' expression in the former equations. But what if v(n1) = v(n2) and v(n1)  VF > v(n3)? In this case, the logical expression equates to unity as u(v(n2)  v(n1)) is zero, but the second part, ( 1  u(v(n1)  VF v(n3)))), will be true  for D1 and D2. Thus BOTH diodes will conduct for this condition.
This appears to be much simpler than the previously derived diode equations, hence we will try to implement this function. Figure 2 is a circuit suitable to test this model.
Half wave bridge (positive) test circuit 1
Figure 2
The netlist for this circuit is:
half wave bridge1.ckt
************************
* B2 Spice
************************
* B2 Spice default format (same as Berkeley Spice 3F format)
***** main circuit
V1 N1 0 DC 0 SIN( 0 10 1k 0 0)
V2 0 N2 DC 3 SIN( 0 10 1k 0 0)
R1 13 N3 1e3
R6 N3 0 1K
B1 N1 13 v = 1 +u(u(v(n2)  v(n1)) + ( 1  u(v(n1)  1 v(n3))))*(v(n1)  v(n3)  1)
B2 N2 9 v = 1 +u(u(v(n1)  v(n2)) + ( 1  u(v(n2)  1 v(n3))))*(v(n2)  v(n3)  1)
R2 9 N3 1e3
.OPTIONS gmin = 1E12 reltol = 1E3 abstol = 1pa vntol = 1uv
+ itl1 = 500 itl4 = 500 method = gear rshunt = 1G
.TRAN 10u 2m 0 1u
.IC
.END
Several items are worth noting at this point. First, the resistors R1 and R2 are essential to the model. Second, the resistors cannot be made much smaller than shown without causing convergence problems. (1 milliohm seems to be a small enough value for most purposes). Third, the VB value used in this text for the diode 'ON' voltage was set at 1 volt, to clearly illustrate its effect in the graphs shown later, however it could be set to zero). Fourth, the step limit was set to 1u sec to give a good plot resolution. Fifth, the integration method was set to 'gear', which often provides a more robust solution method.
A graph of the output is shown in Figure 3 following:
Half wave bridge (positive) test circuit 1 graph1
Figure 3
The graph shows the bridge conducts as expected, with slightly less than 360 degrees of conduction due to the effects of the nonzero value of 1v chosen for VF. The peak value of voltage at N3 of 9v shows the effect of VF being set at 1v.
Just to ensure that the circuit is working VF can be set to zero, and a capacitor of 100 uF added across the load resistor. The effect of just the added capacitor is shown in the graph of Figure 4.
Half wave bridge (positive) test circuit 1 graph2
Figure 4
This plot is as expected, and the added curve of the current through D1 (B1 voltage source current) shows an impulsive current of about 800 ma flows at startup. Diode D1 current shows that it subsequently conducts with a small duty cycle. It is worthwhile to experiment with the circuit to see the effects of adding Equivalent Series Resistance (ESR) to the filter capacitor, varying values of VF and other modifications.
NOTE: If one were to plot D1 and D2 currents, it would seem at first glance that the diode currents were unbalanced, however, realizing that D1 has an impulsive current and D2 does not and also that the D1 and D2 current plots have different 'y' axis scales, it is seen that after the initial transient startup the currents are identical.
One could also model the circuit using the first realization method (nonconducting diodes unless the conduction conditions are met). This is left as an exercise for the reader.
All there is left to do now is to create a parameterized subcircuit part of the diode only portion of the circuit, as well as create a suitable graphic representation of the device. The passed parameters could be just VF, but it might be useful to also have a value passed for resistors R1 and R2. The default value for VF is somewhat arbitrary, whereas that of resistors R1 and R2 should not be much less than 1 milliohm.
This is also left as an exercise for the reader, but it is assumed that this parameterized subcircuit part and an appropriate symbol will be added to the standard library by the B2 SPICE persons, sooner or later, to enable uniform and consistent part usage by users.
'Negative' Bridge realization:
Having tried (hopefully with some success) to clearly show the steps in the 'positive' half wave diode bridge implementation, the realization of the 'negative' implementation will now be done in a much more abbreviated manner. However, some thought will be required.
One cannot just reverse the sense of the B1 and B2 voltage generators from that of the previous model in order to achieve the 'negative' realization. Indeed, the 'sense` of these generators in the model is largely immaterial if the underlying voltage generator equation is correct. The only effect this would have in that event would to change the sense of the plotted currents through the equivalent diodes (a plot of B1 or B2 currents).
But to keep the current sense correct the model I choose to implement will not reverse the generator polarities. The underlying equations must be slightly modified as well to reflect the conduction and nonconduction conditions. For the 'negative' half wave bridge, the voltage equation for diode D1 is:
V = VF +u(u(v(n1)  v(n2)) + ( 1  u(v(n3)  VF v(n1))))*(v(n1)  v(n3) + VF)
The similar expression for diode D2 is:
V = VF +u(u(v(n2)  v(n1)) + ( 1  u(v(n3)  VF v(n2))))*(v(n2)  v(n3) + VF)
The corresponding schematic is shown in Figure 5 following:
Half wave bridge (negative) test circuit 1
Figure 5
In this circuit the value for VF was set at 1v as in the previous example.
The corresponding netlist for this circuit is:
half wave bridge.ckt
************************
* B2 Spice
************************
* B2 Spice default format (same as Berkeley Spice 3F format)***** main circuit
V1 N1 0 DC 0 SIN( 0 10 1k 0 0)
V2 0 N2 DC 3 SIN( 0 10 1k 0 0)
R1 13 N3 1e3
R6 N3 0 1K
B1 N1 13 V = 1 +u(u(v(n1)  v(n2)) + ( 1  u(v(n3)  1 v(n1))))*(v(n1)  v(n3) + 1)
B2 N2 9 V = 1 +u(u(v(n2)  v(n1)) + ( 1  u(v(n3)  1 v(n2))))*(v(n2)  v(n3) + 1)
R2 9 N3 1e3
.OPTIONS gmin = 1E12 reltol = 1E3 abstol = 1pa vntol = 1uv
+ itl1 = 500 itl4 = 500 method = gear rshunt = 1G
.TRAN 10u 2m 0 1u
.IC
.END
Validation and testing of this model is left as an exercise for the reader.
This circuit can and should be made into a parameterized subcircuit. Note: As the sense of the B1 and B2 generators was left unchanged, and the passed VF value is positive as before. It is expected that BB will create a parameterized subcircuit and symbol for this device in the interests of uniformity, and again the values of VF and the resistors R1 and R2 will be passed parameters, with appropriate default values.
Conclusions:
A half wave diode bridge, (nearly ideal when VF is passed as 0.0v) has been created, for both senses of the output. This adds more behavioral models to our available parts for selection in modeling. This model should be capable of addition to any SPICE3 product. If the product DOES directly support behavioral expressions, these could be easily modified to incorporate these devices.
FullWave Bridge
Summary: In previous articles of this series I showed how to create an implementation of a semi ideal half wave bridge. Here we will create what I call a semiideal full wave bridge.
Ideal Full Wave Bridge (FWB1):
A full wave bridge circuit consists of four interconnected diodes. Now it might seem possible and desirable to use 4 ideal diodes to realize the device, as shown in Figure 1 following, and this is possible but this creates simulation problems. That realization would have too many loops possible where ideal sources are interconnected. Moreover, it is overly complex.
Figure 1
Possible Full Bridge realization
A better and simpler realization is to use logical expressions to implement the device. Because the bridge is ideal, the output device should have a voltage output which is the absolute value of the input voltage. However, such a device would NOT be conservative. That is, the output loading would not be reflected to the input. Consequently, we must be a little careful in our implementation. The approach chosen is shown in Figure 2 following:
Figure 2
Full Bridge realization
In Figure 2 there are two implementations of the B2 device equation shown, one for version 4, and the second for version 5.1.5+. The B1 device is suitable for use in either case. Operation of the circuit is straightforward. Generator B1 applies the absolute value of the input AC voltage applied between IN1 and IN2 terminals to the ammeter AM1 and the load.
Resistor R1 is provided to allow a circuit ground to be applied at either the IN2 or the Von output negative terminals. The B2 generator applies an appropriate current to flow at the input terminals. If the voltage from IN1 to IN2 is positive, then the current measured by the ammeter is positive and this value is used. If the input voltage is of the opposite sense, the negative of the ammeter current is applied at the input terminals.
An ideal diode U1 is shown in series with the output terminals. This is required to prevent the output from discharging through the generator.
A test circuit for this realization is shown in Figure 3 following:
Figure 3
Full Bridge test circuit #1
Devices V2 and V3 are provided for test purposes to prevent nodes IN2 and Von being renamed should a ground be present at the V1 input of the Von terminals before it is turned into a subcircuit. Without them the internal nodes would be renamed necessitating some changes in the device equations. V1 is a 10V, 1KHz sine wave. C1 is supplied with a 40 milliohms ESR for a little realism. NOTE that the integration method used is GEAR, which should always be used if sharp switching diodes are present or are simulated.
Below the circuit is an identical circuit where the Full Bridge device has been turned into a part.
A graph of the output of Figure 3 is shown in Figure 4 following:
Figure 4
Full Bridge test circuit #1 graph
Here we see that the conduction angle is short. Because of the ideal components, there is a sharp pulse of current at the start of each conduction cycle. Because of sampling effects, the GRAPHED values will vary a bit, and could be checked by using a smaller value of step ceiling in the test, but the other values of interest are correctly shown. After this pulse, the current will decrease as the charge on the output capacitor is replaced until the voltage present at the output exceeds the rectified drive to the load.
The portion of the circuit with the newly created PWL1 part is graphed at the bottom of Figure 4, and it behaves as does the top portion of the circuit it is based on.
Conclusions:
A half wave diode bridge circuit has been created. This adds more behavioral models to our available parts for selection in modeling. This model should be capable of addition to any SPICE3 product. If the product DOES directly support behavioral expressions, these could be easily modified to incorporate these devices.
erroramp2
Summary: In previous articles of this series I showed how to create logical expressions. In this blurb I show how to prepare an error amplifier model useful with SMPS controller chips. There will be another error amplifier model (erramp) prepared for that set of articles, however in some ways this model is more suitable.
Erramp2:
Why would one wish to create such a circuit? Often when one uses a behavioral model for a device (particularly IC realizations), the linear range of the device is unlimited. But in the 'real' circuit the voltage excursions cannot exceed the power supply 'rails'. Now one could use a 'real' opamp model, but it will add to the complexity of the overall circuit and will simulate slowly. And the 'real' opamp chosen may also not represent the actual device implementation within a controller chip, and it might not work well with the internal voltages within the controller chip as well. Indeed, most of the parameters of the internal amplifier might be poorly specified on the controller chip data sheet.
Yet, for current mode SMPS controller chip modeling, the error amplifier gain is a crucial parameter. And often the voltage excursions of the error amplifier are important as well. Alternately, even when the error amplifier (or compensation amplifier) is external to the controller one may wish to use a simplified model to ease simulations. Consequently, erramp2 was created to produce an error amplifier with a controllable gain, as well as voltage excursion limits. I might have also chosen to include an RC voltage divider at the output to limit the gain bandwidth, but this would have added some complexity. As the model was chosen primarily to be used within SMPS controller chip realizations, which themselves be turned into a subcircuit, it did not seem necessary to include this as they could easily be added externally to the error amplifier.
Erramp2 model:
There are several ways the device could have been modeled. I could have used a controlled gain error amplifier. The excursions could have been limited by clamping the output with a bilateral clamp circuit, or a feedback element could have been devised which would limit the output voltage levels. It seemed easier to implement it directly with logical expressions.
What I chose to do is to determine the possible output states and devise equations to represent those states. The expressions themselves could have been written in several ways, however, as no real simplification seemed evident, and the model did work as intended, alternate implementations were not explored.
Consider a simple opamp model with a noninverting input Va, an inverting input Vb, and an output Vo. Excluding such effects as slew rate limiting, five states are evident. They are:
1. Va = Vb
2. Va > Vb, but we are within the linear region
3. Va > Vb, but the product of gain and (Va  Vb) is greater than Vopl
4. Vb > Va, but we are within the linear region
5. Vb > Va, but the product of gain and (Va  Vb) is less than Voml
Vopl is the maximum positive output voltage limit, and Voml is the negative output limit.
Inspection of the states reveals that states 2 and 4 are are the same, governed by the same result, namely Vo = G(Va  Vb). Moreover, state 1 is a subset of this state.
The equations we wish to create, three in all, are as follows:
IF (Va>Vb) and G(Va  Vb) > Vopl THEN Vo = Vopl
ELSE
IF (Vb>Va) and G(Vb  Va) > Voml THEN Vo = Voml
ELSE
Vo = G(Va  Vb)
The equations thusly combined, become:
Vo = IF (Va>Vb) and G(Va  Vb) > Vopl THEN Vo = Vopl  G(Va Vb)
+ IF (Vb>Va) and G(Vb  Va) > Voml THEN Vo = Voml  G(Va  Vb)
+ G(Va  Vb)
To be honest, it took a little bit of time and effort to create these expressions in their final form, as shown in the results in Figure 1 following:
Figure 1
Erramp1 circuit model
In this circuit the values which will eventually become passed parameters are shown in the equation for B3 generator as constants. A suggested symbol for this device is also shown.
A test circuit for this model is shown in Figure 2 following:
Figure 2
Erramp2 test circuit
There are actually two instances of erramp2 in this test circuit. What happened is that I debugged the erramp2 circuit, and them created a parameterized subcircuit model of the device which I then placed into the circuit. As there are some editing changes required to create the parameterized subcircuit model, it seemed appropriate to include this here, to compare the output results and insure that no mistakes were made in creating the parameterized subcircuit model. The parameterized subcircuit is shown as a subcircuit in the netlist while the model is shown under the main heading.
A netlist for this circuit (remembering that there are two instances) is:
limited finite gain erroramp.ckt
************************
* B2 Spice
************************
* B2 Spice default format (same as Berkeley Spice 3F format)***** subcircuit definitions*limited finite gain erroramp.ckt
************************
* b2 spice
************************
* b2 spice default format (same as berkeley spice 3f format)
* created by harvey morehouse
*
* this model was created for use in smps current mode controller chips where the error amplifier
* gain is an important parameter.
*
***** main circuit
.subckt erramp2 va vb n1
*   
*   output
*  inverting input terminal
* noninverting input terminal
*
* set the bandwidth using an external rc voltage divider(s) at the output
*
* if the voltage difference between va and vb is comparatively large the ckt may produce
* unexpected results. do not use this model as a comparator.
*
b3 n1 0 v = u(v(va) v(vb))*(u( 3.100000e+004 *(v(va)  v(vb))  5.000000e+000 ))*( 5.000000e+000  3.100000e+004 *(v(va)  v(vb))) + u(v(vb) v(va))*(u( 3.100000e+004 *(v(vb)  v(va)) + 5.000000e+000 ))*( 5.000000e+000  3.100000e+004 *(v(va)  v(vb))) + 3.100000e+004*(v(va)  v(vb))
r1 va vb 1e9
r4 n1 0 1meg
.ends erramp2***** main circuit
B3 N1 0 v = u(v(va) v(vb))*(u(31000*(v(Va)  v(Vb)) 5))*(5 31000*(v(Va)  v(Vb))) + u(v(vb) v(va))*(u(31000*(v(Vb)  v(Va)) 3))*(3 31000*(v(Va)  v(Vb))) +31000*(v(va)  v(Vb))
R1 Va Vb 1e9
R4 N1 0 1K
V1 Va Vb DC 0 SIN( 0 .001 100k 0 0)
XX1 Va Vb N2 erramp2
R3 Vb 0 1e9
.OPTIONS gmin = 1E12 reltol = 1E4 itl1 = 500 itl4 = 500
+ rshunt = 1G
.TRAN 10u 20u 0 .0001u
.END
Note that in the parameterized subcircuit, the default values for G, Vopl and Voml are passed to the netlist.
Figure 3
The result of the simulation
They behave as expected, in that the linear region is centered about the zero crossings of the input sine wave. An astute observer will see that the N1 and N2 outputs have different amplitudes. This resulted from different values of Voml used in the test circuit than those set as default parameters in the parameterized subcircuit model.
It is interesting to see what the effects are of using larger and larger values of input voltage. Eventually unexpected results will occur, due I suspect from numerical solution errors. However, the circuit is intended for use imbedded within a feedback loop, and not as a comparator. Consequently when the Va  Vb difference is small the results are as expected.
Conclusions:
An error amplifier model suitable for use within SMPS controller chip models has been created. It features a controlled gain, as well as settable output voltage excursion limits. By addition of external RC and other devices, external to the model, or by their addition within another parameterized circuit model if desired, its utility
OTA1
Summary: In previous articles of this series I showed how to create logical expressions. In this blurb I show how to prepare an Operational Transconductance Amplifier model useful with SMPS controller chips.
OTA1:
An OTA is a voltagetocurrent amplifier. Its operation is similar to that of a vacuum tube, or a voltage to current controlled source. It is not a popular device, but several interesting devices are OTA devices and this device is also used within many interesting chips. While one could use a voltage to current controlled source with realizations, a unique device with its own symbol highlights the design difference of this device. Several OTA implementations have another input. At a later time this will be incorporated as an OTA2 device type.
OTA1 Model :
Figure 1 following shows the OTA1 device model, together with its symbol.
Figure 1
OTA type 1 circuit model
Source B1 has a transconductance value which is passed to the parameterized subcircuit, as are the values of R2 and C1. R2 and C1 establish the AC characteristics of the device.
A test circuit for this device is shown in Figure 2 following:
Figure 2
OTA type 1 test circuit
In Figure 2 two instances of an OTA type 1 are shown, one with the circuit implementation in a test configuration and the second with a parameterized subcircuit model. A graph of the output of this device with an AC frequency sweep is shown in Figure 3 following:
Figure 3
OTA type 1 test circuit
Clearly from Figure 3 the output voltages in DB and their phase, for out2 and out3 coincide. The circuit is so simple no netlist is required.
Summary:
An OTA circuit, type 1, has been prepared which may be useful in some simulations. Some precautions must however be used. The circuit is meant to be used in a closed loop configuration, as with large differential voltage inputs it will not accurately represent the operation of the device. This occurs because the real device output voltage and currents are limited, unlike that of the model. However for many applications this device is well suited to represent an OTA type 1.
NO Smooth Switches: Part 1
Summary: In this article I describe now to make a smooth switch model, Smooth Transition Switch Type 1 (STSNOT1). Also included is a means for producing a simple current limited voltage source.
Smooth Switches:
Often one wishes to model a transistor using a switch model to represent it, either to simplify the analysis and/or when the switching device characteristics are not well known and its performance is nonetheless very rapid, especially compared the time constants of the rest of the circuit. Even when modeling a real switch, but the switch characteristics are not well known with regards to switch bounce, arcing and other characteristics of the real switch, and/or these characteristics are not important to the simulation, a fast simulating model is desired.
When a typical switch model provided as a default with many SPICE products opens or closes, it represents an impedance which virtually instantaneously changes from a very low to a very large impedance. This often creates convergence problems for many simulations. This occurs because the SPICE engine often is running at large step intervals just before the switch activation, and it tries to step over the switch event. So at best, it gears back down to a very small step interval. Worse, occasionally it finds a stable solution at the large step interval, and creates an erroneous solution.
What is desired is a switch that will change between an 'off' or 'open' high resistance state to an 'open' or 'on' resistance state in a smooth manner. In one sense it is still discontinuous, as it's state does change abruptly, however, its impedance about the switching interval changes in a very small amount, and also for small changes within the switching interval.
STSNOT1:
One of the simplest smooth switch models which smoothly switches is shown in Figure 1 following:
Figure 1
STSNOT1 switch model
This model is very simple. A control voltage is applied between N3 and N4 terminals, and the switch contacts are represented by the circuitry between nodes N3 and N4. Generator B1 applies a current between nodes N1 and N2 which is dependent on the voltage between nodes N3 and N4. Specifically, for the B1 source, its current value is set as :
i = u(v(n3,n4).1)*v(n1,n2)
This means, that IF the control voltage is GREATER than 0.1 volts, the switch point, the current through the switch (neglecting the contribution of the 'OFF' resistance R2) will be equal to the voltage across the switch control terminals. This presents a resistance which is equal to 1/(v(n3,n4)  in parallel of course with R2, and it varies from 1e6 ohms to about 1/max(v(n3,n4).
Consequently, with the control voltage very slightly below 0.1V, the switch current is v(n1,n2)/R2. With v(n3,n4) very slightly in excess of 0.1 volts, the additional current is very slightly more than v(n1,n2)/R2. With increasing v(n3,n4) the switch current becomes greater until v(n3,n4) and v(n1,n2) reach stable points (the external circuit permitting, of course) when it presents a current of v(n1,n2)/Vmax(v(n3,n4)0.1). Thus if v(n3,n4) reaches 10 volts, then its final resistance value becomes approximately 1/10 ohms. A test model of this circuit is shown in Figure 2 following:
Figure 2
STSNOT1 test circuit #1
The test circuit is quite straightforward. V1 is a pulsed 5V source, 50% duty cycle, with a 1p sec rise and fall time and a period of 0.02u sec. This voltage is integrated by R5 and C1 to form a smooth ramp. Now this is not realistic to drive a 'real' mechanical switch or even to simulate most transistors, but it illustrates the action of the switch, which is shown in Figures 3 and 4 following:
Figure 3
STSNOT1 test circuit fall time graph
Figure 4
STSNOT1 test circuit rise time graph
Suppose however the control signal is a circuit with a final level of 1 volt, and one wishes a final switch on resistance of 125m ohms? In that case, solve the following equation:
1/k*(max(v(n3,n4)von) = Ron
Using Ron = .125, von = .1, max(v(n3,n4)) = 1, one arrives at the relation that:
1/k*.9 = 0.125
Solving for k:
k = 1/0.125*.9 = 8.88889
checking now:
1/8.888889*.9 = 1/8 = .125 ohms
In this case then one can edit the model to multiply the B1 source to multiply the uramp function by 8.888889.
I considered making a parameterized subcircuit model for this device, and including an RC network into the model, but it is such a simple device, that if one needs a source with a specific rise time control signal one can externally add it as needed. And, as most of my logical device digital models where I would use generally such switches have RC networks at the output, these could be modified if required to tailor the switch characteristics as required. Thus, only a subcircuit model for this device was created.
However, the switch itself needs some more testing. The most important case (for me) is where the switch is driving a capacitive load, and where the load capacitance behaves as an infinite capacitor over a range. This is the case for a diode, where it takes time to switch the diode from a conducting state to a nonconducting state. During the reverse recovery time it presents an essentially constant 'ON' voltage until the excess charges are swept out of the device. This application is best illustrated in the case of a simple model of a BUCK converter. A test circuit is shown in Figure 5 following:
Figure 5
STSNOT1 test2 circuit 1
In this circuit the switch represents a switching transistor in a BUCK converter model. The BUCK converter itself is shown as open loop, to simplify the test circuit. In this circuit, the switch is not the STSNOT1 model, but is the standard 'instantaneous' switch device provided in the standard library. A small portion of the output is shown in Figure 6 following:
Figure 6
STSNOT1 test2 circuit1 graph
This shows the problem in using a nonsmooth switch, as the V2 currents (pink trace) show large spikes when the switch is turned on.
Now as a first pass, one could attempt to use a current limited source, as the spikes of 30A are clearly not right. Of course one could just ignore them, but that is cheating. Let us add a simple current limiter. This is shown in Figure 7 following, with the addition of a diode and a current source connected as shown.
Figure 7
STSNOT1 test 3 Circuit
The operation of the current limiter, composed of current source I1 and ideal diode U1, is straightforward. I1 biases the diode on with a current of 3A in this case. V2 can provide current ( which flows through diode U1) until the net current of diode reaches 3A, in which case the diode then becomes reverse biased, and no greater current will flow. One can test this circuit separately, and see that it does work in simple cases. Let us see if this will limit the spike of current, or at least limit them, through v1, S1 and D1. A test graph of this circuit is shown in Figure 8 following:
Figure 8
STSNOT1 test 3 Circuit graph
In this case the v2 current still spikes at about 30A, even with the current limiting using an ideal diode. As a test, a second ideal diode will be used to replace diode D1. This model will switch faster than any 'real' diode device, so it will be interesting to see what happens. This is left as an exercise for the reader, but to give away the plot, there is no difference.
We are running into the time limits, the minimum times that the circuit will resolve, as well as into problems with the behavioral models. (Under SIMULATIONS, SETUP, set the maximum step size to 1u. This helps convergence.) With such ideal elements there is just no way that a solution can be found that is ideal under the conditions of using a switch that transitions in about zero time.
Note also that the open loop circuit is quite underdamped, depending of course on the size of the load resistor. The circuit consisting of the inductor, output capacitor and ESR of the capacitor tends to be fairly high 'Q', with the load resistor and ESR resistance providing damping. Thus, because of the ringing, some rather strange effects can occur depending on the values chosen. This is however extraneous to this paper, as the purpose here is to insure the switch model may be used effectively.
Now, however, using the same circuit but with the smooth transition switch device and the ideal diode D1, we arrive at the circuit in Figure 9.
Figure 9
STSNOT1 test 3 Circuit
In this circuit the smooth transition switch, which has been turned into a device (ST1), is used. A graph of the circuit output is shown in Figure 10 following.
Figure 10
STSNOT1 test 3 Circuit graph 1
Here we can see that the large current spikes have been minimized. In truth, there will and should be some current spikes with a real converter, unless of course one is using a similar circuit in a critical conduction mode or discontinuous conduction mode.. That is to say, if the switch drive and load are such that the conduction time/duty cycle of the switch is small and the current through the inductor and the flywheel diode drops to zero during the switch 'OFF' time, the turnon current spiking will be minimal.
Another expanded view of a portion of the same graph is shown in Figure 11 following:
Figure 11
STSNOT1 test 3 Circuit graph 2
Here we can see that the diode turns off in about 6 ns. Notice that it is conducting (the voltage v(n2) is slightly negative before the transition. From Figure 10 we can see that voltage at v(n2) is about 10 volts, hence it is off when the source v2 is charging the inductor.
Now it is interesting to investigate to see the effects of the control voltage rise times on the current spike. Using the same circuit as in Figure 10, but with rise and fall times of 2us, and a dwell of 0.5us, we get the graph as shown in Figure 12 following:
Figure 12
STSNOT1 test 3 Circuit graph 2
Here we see that the current spike is reduced somewhat. The inductor current waveforms have changed slightly as have the other waveforms, not to mention the dynamic behavior of source B1 (within the switch model) due to the slight waveform difference.
As can be seen, the waveforms of switch current are not as nice and well behaved as we might like, however, if the design is appropriately performed, just as with a transistor, in a feedback configuration, the variances of the switch or transistor are made of no great effect. In this case, if the switch or transistor time constants are reasonably small compared to the rest of the circuit, their effects will not be great.
As you will see if you make the models and perform the simulations, they take a long time to simulate. And however much time it takes for the open loop buck converter we have used here to simulate, addition of a controller chip with a modulator, error amplifier, comparator and other circuitry could add considerably to the simulation time.
This device is very useful for most simulations; however, it does have its limitations. It would be nice if we had a switch which would vary in a logarithmic manner between off and on states. It would be nice if we had more control over the switch state behavior rather than relying on the external drive. Other switch models are possible which are more flexible and present better behavior for other situations, and may be presented later. However, it is always possible to edit the switch model in a given simulation to modify its characteristics.
Conclusions:
A smooth switch model was created which can be used in simulations in place of transistors or abruptly varying switches to ease simulation times and aid in circuit convergence. The use of this model within a primitive Buck switching circuit is shown. A means of providing simple current limiting to a power supply level is also provided.
Smooth switch models of this type have been around for ages.
References:
1: PCBCafe.com Online Book. http://www10.pcbcafe.com/book/parse_book.php?article=SMPS%2F%!intro.htm
2. Charles Hymowitz Generic switch model. http://www.edn.com/contents/images/DI1149.txt
NO Smooth Switches: Part 2
Summary: In this article I describe now to make a smooth switch model, Smooth Transition Switch Type 2 (STSNOT2).
Smooth Switches:
In the previous article a rather lengthy discourse was provided. It is assumed that the reader is familiar with that article hence this article will be much briefer, as the model is similar as are the test circuits. Here an exponential approximation is used to vary the switch model 'resistance' within the switching range.
Because of this, even when 'ON' and 'OFF' points are set for input voltage
levels where the switch is fully on, and fully off, the switch will not
usually show large changes at these levels. However they define the region
where the transitions will occur as being somewhere within those levels,
depending on definition as well as the shape of the input waveform and
the nature of the external circuitry as well.
STSNOT1:
This switch model which smoothly switches is shown in Figure 1 following:
Figure 1
STSNOT1 switch model
This model is very simple. A control voltage is applied between N3 and N4 terminals, and the switch contacts are represented by the circuitry between nodes N3 and N4. Generator B1 applies a current between nodes N1 and N2, which is dependent on the voltage between nodes N3 and N4, as well as the voltage between nodes N1 and N2.
Specifically, for the B1 source, its current value is set as:
i = (1u(v(N3,N4) 1))*v(N1,N2)/1e6 + u(v(n3,n4)4)*v(N1,N2)/.1 +
(1u(v(N3,N4)4))*u(v(N3,N4)1)*V(n1,N2)/(EXP(LN(((.1*1e6)^.5)) +
3 * LN((.1/1e6)) * (V(n3,n4)  ((4+1)/2)) / ((2* (41))) 
2 * LN((.1/1e6)) * (V(n3,n4)  ((4+1)/2))^3 / ((41)^3)))
This equation was taken from reference 1, with some slight modifications. The equation covers three regions of operation. Later, this will become a parameterized equation (as per reference 1) however we wish to test it first and explore its operation. Consequently, Ron is represented by a value of 0.1 ohms, Roff by 1e6 ohms, Von by 4 volts, and Voff by 1 volts. Von should be greater than Voff.
The first region is where the input control voltage is equal to or less than Voff, and is comprised of the term:
(1u(v(N3,N4) 1))*v(N1,N2)/1e6
Here the portion u(v(N3,N4) 1) tests to see if the input control voltage is greater than Voff. (Please refer to the 'logic' articles at the B2SPICE web page under RESOURCES if this is not clear.) This function will return a value of 1 if the condition is true, and zero if it is false. Subtracting this value from unity will produce a function that will be true IF the control voltage is NOT greater than Voff. In that event, the current through terminals N1 and N2 will be equal to the voltage across terminals N1 and N2 divided by Roff
The second region is described by the term u(v(n3,n4)4)*v(N1,N2)/.1. Here the test performed by term u(v(n3,n4)4) determines if the control voltage is greater than Von, and if so, the current through terminals N1 and N2 is set by the voltage across those terminals divided by Ron.
The third region is intermediate between those regions, where the control voltage is greater than Voff, but less than or equal to Von. The region is defined by the term (1u(v(N3,N4)4))*u(v(N3,N4)1). In that case the current through terminals N1 and N2 is set as the voltage across those terminals divided by a resistance defined by the remainder of the equation.
A test model of this circuit is shown in Figure 2 following:
Figure 2
STSNOT2 test circuit #1
The test circuit is quite straightforward, however translating and typing the equation into a working form was a chore. To simplify the operation, sources B4, B5 and B2 were used to simplify the typing and keeping track of the brackets. They represent the three regions of operation previously described. Initially the value for B1 current was set to be I = v(7) + v(14) + v(12) until debugging was completed, whereas in the final form the terms were directly entered into B1 source. The final model includes only the B1 source.
(An astute reader might notice the presence of sources V3 and V4 and wonder what purpose they serve. What they do is to isolate the nodes N4 and N2 from ground, allowing the equations used in the circuit to remain without renaming them to node 0. The sources are zero volts, similar to the ammeter model, which isolate nodes while allowing them to be electrically identical. This technique is also usable in creating a chip model where several instances of a circuit point are brought out to two or more external pins. Now one could use a very small resistance to the same effect, but this is more elegant.)
B2 was a test source used to examine some of the individual logic operations used in B3, B4 and B5 models during realization of the model. V1 is a pulsed 5V source, 50% duty cycle, with a 1p sec rise and fall time and a period of 0.02u sec. This voltage is integrated by R5 and C1 to form a smooth ramp. Again this is not realistic to drive a 'real' mechanical switch or even to simulate most transistors, but it illustrates the action of the switch, which is shown in Figure 3 following:
Figure 3
STSNOT2 test circuit fall time graph
The yellow trace shows a smooth transition of voltage across the switch, the N3 terminal voltage.
The switch itself needs some more testing. The most important case (for me) is where the switch is driving a capacitive load, and where the load capacitance behaves as an infinite capacitor over a range. This is the case for a real diode and a good model, where it takes time to switch the diode from a conducting state to a nonconducting state. During the reverse recovery time it presents an essentially constant 'ON' voltage until the excess charges are swept out of the device. This application is perhaps best tested in the case of a simple model of a BUCK converter. A test circuit is shown in Figure 4 following:
Figure 4
STSNOT2 test2 circuit 2
In this circuit the switch represents a switching transistor in a BUCK converter model. The BUCK converter itself is shown as open loop, to simplify the test circuit. A small portion of the output is shown in Figure 5 following:
Figure 5
STSNOT1 test2 circuit2 graph
Here we can see the expected sawtooth current in the inductor after all of the transients are essentially over. There is a small current spike through the v2 source when the switch turns on, which is to be expected (the orange trace).
As you will see if you make the models (or they are included in the library) and perform the simulations, they take a long time to simulate. And however much time it takes for the open loop buck converter we have used here to simulate, addition of a controller chip with a modulator, error amplifier, comparator and other circuitry could add considerably to the simulation time. Using other than behavioral devices would take even longer. It is important to use the fastest computer possible with lots of memory for SMPS simulations. This model will be converted into a parameterized subcircuit part, and hopefully will be added to the B2SPICE standard library.
NOTE: Occasionally in using this model one will see exponent error notations, where an exponent is to large to be resolved. This occurs because the logical functions as implemented in B2SPICE are not true IF… THEN …. ELSE functions, in that all of the terms will be resolved and calculated. Unlike such a function written in 'C' code, where if specified else conditions are met, the remaining ELSE functions are ignored, they are resolved here. However, these conditions are in the denominator of a function, and result in a '0' (or nearly so) final calculation. Consequently these conditions may be safely ignored, as they will not affect the final calculations.
Conclusions:
A smooth switch model was created which can be used in simulations in place of transistors or abruptly varying switches to ease simulation times and aid in circuit convergence. The use of this model within a primitive Buck switching circuit is shown.
References:
1: PCBCafe.com Online Book. http://www10.pcbcafe.com/book/parse_book.php?article=SMPS%2F51intro.htm
B2.Spice A/D Gates
Summary: In previous articles I created several logic devices (AND, NAND, OR, NOR, INVERT, that were not parameterized. These were created in version 4. While they will work correctly, their not being parameterized created several little problems for me. Here we will create parameterized subcircuits for these devices, suitable for use within other parameterized subcircuits. It is intended this will replace those devices within the version 5 library, which were ported over to version 5.
Basic Logic Devices:
The basic logic devices to be parameterized are shown in Figure 1 following:
Figure 1
Basic logic gates
Version 5 models:
AND2:
The AND2 device model is shown in Figure 2:
Figure 2
V5 AND2 Circuit
The parameterized equation for B1 generator in what will become the AND2 device is shown in Figure 1, together with the parameters to be passed and their default values. A test circuit is shown in Figure 3.
Figure
3
V5 AND2 test Circuit
Here we are stimulating the circuit with two pulsed voltage sources, each of which having an RC circuit load to simulate the output of a gate of some sorts. A graph of the circuit outputs is shown in Figure 4 following:
Figure
4
V5 AND2 test Circuit graph
There are no surprises in this circuit. All works as expected. There ARE some 'slivers' in the outputs, but this is to be expected, as the inputs will occasionally be such to produce them.
AND3:
The
AND3 circuit is very similar to the AND2 circuit, with just another
term added to account for the third input. The circuit is shown in
Figure 5 following:
Figure 5
V5 AND3 Circuit
The AND3 test circuit is again similar to that of the AND2 circuit, and is shown in Figure 6 following:
Figure
6
V5 AND3 test Circuit
A graph of this circuit output is shown in Figure 7 following:
Figure
7
V5 AND3 test circuit graph
Here we see the expected results. The generator periods were chosen deliberately to create all possible combinations of input signals, and naturally enough there are again some slivers. However, expanding the graph shows that the slivers are appropriate for the input signal conditions.
NAND2:
A NAND gate is a simple variation of an AND gate, with the THEN and the ELSE conditions transposed. This is shown in Figure 8 following:
Figure
8
V5 NAND2 Circuit
The test circuit for this device is shown in Figure 9 following:
Figure
9
V5 NAND2 test circuit
A graph of the circuit output is shown in Figure 10 following:
Figure
10
V5 NAND2 test circuit graph
The NAND2 device works as expected. When both inputs are HIGH, the output is low.
NAND3:
The NAND3 device is just a variation on the AND3 device. The NAND3 model is shown in Figure 11 following:
Figure
11
V5 NAND3 circuit
The test circuit for this device is that for the AND3 circuit, with the exchange of the VOl and VOh terms in the B1 generator.
Figure
12
V5 NAND3 test circuit
The graph of the circuit output is shown in Figure 13 following:
Figure
13
V5 NAND3 test circuit graph
Here we see the NAND3 circuit is well behaved.
OR2:
An OR2 circuit is shown in Figure 14 following:
Figure
14
V5 OR2 circuit
A test circuit for this device is shown in Figure 15 following:
Figure
15
V5 OR2 test circuit
A graph of this circuit output is shown in Figure 16 following:
Figure
16
V5 OR2 test circuit graph
Again the circuit behaves nicely.
OR3:
An OR3 device was not provided for version 4, but for completeness, it is included here. The circuit is as shown in Figure 17 following:
Figure
17
V5 OR3 circuit
The OR3 test circuit is shown in Figure 18 following:
Figure
18
V5 OR3 test circuit
The graph of this circuit is shown in Figure 19 following:
Figure 19
V5 OR3 test circuit graph
NOR2:
The NOR2 circuit is shown in Figure 20 following:
Figure
20
V5 NOR2 circuit
The NOR2 test circuit is shown in Figure 21 following:
Figure
21
V5 NOR2 test circuit
A graph of the test circuit output is shown in Figure 22 following:
Figure
22
V5 NOR2 test circuit graph
NOR3:
The NOR3 circuit is shown in Figure 23 following:
Figure
23
V5 NOR3 circuit
The test circuit for this device is shown in Figure 24 following:
Figure
24
V5 NOR3 test circuit
The graph for this circuit is shown in Figure 25 following:
Figure
25
V5 NOR3 test circuit graph
INV:
An inverter circuit is shown in Figure 26 following:
Figure
26
V5 INV circuit
A test circuit for this device is shown in Figure 27 following:
Figure
27
V5 INV test circuit
The graph of this device is shown in Figure 28 following:
Figure
28
V5 INV test circuit graph
These devices have been tested previously and they work as expected. Consequently no tests will be performed here.
Summary:
A
set of parameterized devices has been created for two and three input
AND, NAND, OR, NOR devices and an inverter using just a small portion
of the logical expression capabilities of version 5.15+. For those
persons who have followed the logical expression articles, which in
the main have been based on use of the ustep and uramp functions,
it should be clear how much easier it is to create and understand
devices implemented with these functions. These devices will be incorporated
into the version 5 standard library, and should be available at the
next program update following the appearance of this article on the
B2SPICE web site.
B2.Spice A/D Logical Expressions: Part 1
Summary: Version 5.14 has added to/improved the logical expression features of v5.13. While there are a few problems still remaining in the implementation, or lack thereof, these can be overcome without much difficulty. All of the features have not been extensively and fully tested, but the changes are significant and part of the evergrowing capabilities of their product.
Logical Expressions:
Logical expressions are equations/expressions where the result/outputs are binary in nature. That is to say, the result after evaluation of the expression/equation will be bipolar in nature, such as one value or another, or one function/expression will be created as an output or a second one will.
By combining these logical expressions, one can create complex functions, where, dependent of the results of variables or expressions taking on different values, different outputs may be provided.
Logical values are the result of operations by logical expressions or operators, on values produced by logical expressions.
The logical value of a variable or expression, not to be confused with a logical value produced by operations on a variable or expression, is that, if the variable or resultant expression value is greater in magnitude than zero it will be represented as a logic ‘ONE’ and logical ‘ZERO’ otherwise. Certain operators should automatically convert or otherwise interpret variables or expressions as their logical value equivalents where they are not already explicitly defined themselves as logical values.
If you are confused, it is harder to write it than to understand it. Look at it this way. Suppose you had a unary expression such as the ‘~’ or negate operator. This makes no sense to use other than with a logical operand. Consequently, an expression using this operator should have its operand either as a logical value or it should be converted automatically if not. An example of its use with logical operands is:
V = ~(u(v(5)*v(7)) –(v(3)>0))
Now here it is assumed v(3), v(5) and v(7) are some arbitrary real function of time. V(3)>0 clearly returns a logical value. u(v(5)*v(7)) clearly also returns a logical value. These two logical values are subtracted to produce an argument that could have the values over time of +1, 0 or –1. It would still be a logical operand, sort of at least. So, the ‘~’ operator would cause a value to be returned respectively, of 0, 1 and 1 respectively.
Now were the operand not a logical value, what are the implications and what should happen? Suppose the expression were:
V = ~(v(3)*v(5) – v(7))
How would this be operated upon and how should it be? IF one were to use the expression:
V = ~u((v(3)*v(5) – v(7)))
Were v(3), v(5) and v(7) logical values, each produced as the output from another generator or generators with a logical argument there would be no ambiguity. The argument would take on the values of 1, 0, and –1 as possible values. And as before, the output would respectively be 0, 1 and 1.
Now suppose they were not logical values. Unless the expression were evaluated using that assumption, the argument would be meaningless. So if the argument is not composed of clearly logical values as the results of operands or expressions that returned such values, the resultant should be converted. Now the argument for the implied ustep function could be greater than zero, equal to zero or less than zero, which would produce a ustep output value of 1 or 0 respectively. This, operated on by the ‘~’ operator, would produce an output of 0 and 1 respectively. The results are not necessarily the same in either instance, but it makes sense.
When one reads a document, the assumption is that the writer knows what they are doing, at least as a start. Therefore, the expression V = ~(v(3)*v(5) – v(7)) should be interpreted as being equivalent to V = ~u((v(3)*v(5) – v(7))). In fact, if the argument of a ‘~’ function is ALWAYS treated as if there were an implied ustep of the argument, it is a clear and understandable rule. The ‘~’ function is not implemented, and hopefully it will be, but in so doing it should have an implicit ustep function included for its argument. Other functions should also have such an implicit rule.
Logical Expression Primitives:
To be really useful an instruction set should include items such as operators as well as expressions. Some of the operators are unary. Meaning, they are effective with just one operand. This would be the case for a logical negate. Others are useful with two operands. Such would be the case for a logical AND.
Some of the operators that a fullfeatured SPICE with a logical expression format would include are shown in the following:
Type 
Possible Symbol 
Provided 
Alternate 
Comments 
Logical Negate 
'~' 
no 
(1 lval) 
If the variable is logical with just unity and zero possible values, subtracting this variable from unity will be the negated value. 
Logical AND 
'&' 
yes 

Multiplication or 'ANDING' of logical values will produce a unity value when both (or all) are true. This operator works for logical operands but does not work for the logical value of an operand. (See Figure 1) 
Logical OR 
'' 
yes/no 

This works with logical variables, but the logical value of a logical variables cannot be used yet. One can 'OR' two variables and get a 'TRUE' result when either or all are nonzero. (See Figure 2 and Figure 3.) 
Equal 
'==' 
yes/no 

This function works with logical variables but not with logical values of voltages. (See Figure 4.) 
GTR 
'>' 
yes 

This operator for integer and real values would compare the operand to the left of the '>' with that to the right, and produce a unity output if the left were greater, otherwise returning a zero. (See Figure 5.) 
LT 
'<' 
yes 

This operator produces the logical inverse of the GTR function. (See Figure 5.) 
XOR 
'' 
no 

This operator would produce an EXCLUSIVE OR of the two LOGICAL arguments, returning a unity value when just one of the two arguments is true, and zero otherwise. 
uramp, ustep functions 
u(arg), uramp(arg) 
yes 

These functions can still be used as before. 
Table
1
Possible Logical Operators
Some other logical operators could be defined. But as you can see,
MOST of these operators are directly provided. The negate would
be nice, but it can be worked around, either by construction of
the logical expressions or as noted, by subtraction of a logical
variable from unity. The XOR would be nice, but it also is easy
enough to work around in the few cases where it is needed. At best
it would be useful for easing netlist conversion formats from other
SPICE formats to B2SPICE.
There is one other problem. That is, to quote the persons at B2SPICE directly, "I think that they may still fail for logical expressions that require parentheses grouping for overriding operator precedence, but they work for the test cases you sent in.". This takes a lot or work to verify fully and report on all the instances and cases, however, from a very brief look so far, extraneous parentheses or parenthesis groupings not recognized may cause the SPICE engine to choke, as well as perhaps in other cases of grouping of variables into IF .. THEN …ELSE expressions. This will be discussed in a later section.
The first operator to be tested is the AND or '&' function. Refer to Figure 1 following:
Figure 1
AND (&) operator test
The sources V1 through V4 are 1 volt sine sources of 1K, 3K, 5K and 7K frequencies respectively.
Although the operator does not automatically use the logical values of variables and expressions, it apparently is usable in more complex expressions by the use of parenthesis groupings.
The
next function to be examined is the OR operator. The same essential
test circuit is used as in Figure 1.
Figure 2
Logical OR () test
There is of course no graph to present for the fail cases, and the pass cases are really not that interesting. Therefore, it is suggested that the interested reader recreate the Figure 1 circuit and experiment with it.
The rule is that, as presently implemented, only logical variables may be 'OR'ed. But just as in the case of the nonexistent '~' negate operator, it is suggested that an implied ustep of the arguments of each '' operator be provided.
The next symbol to be examined is the EQUATE or' ==' operator. See Figure 3 following:
Figure
3
Logic equate ( ==) usage
The equate function does not work using the logical values of real variables. It will work with logical variables, however. Three or higher level equates seem to fail, as well as, as mentioned in the comments given to me and related earlier, where grouping by parentheses is used to try to change the order of function evaluation.
The rule for the present implementation seems to be that logical functions can be used with the '==' function, but external parentheses are not allowed. Moreover, it seems that the precedence of operators and their evaluation needs to be considered when parsing an expression. As in the case of:
v = u(v(v1)) == (v(v2)>0)
In the above, which fails, it would seem that one would first evaluate the terms to the left and right of the '==' operator, and then use the equate operator. And, were there several instances of the operator, one should start from the right of the last argument, and work to the left. (Lest one wonder, v = u(v(v1)) == v(v2)>0 also fails.)
Next we will look at the '>' and '<' operators.
Figure
4
Logical GTR and LTN (> and <) operator usage
Apparently only variables, not even simple expressions are usable with the < and > operators.
The XOR function, '' is not implemented. The uramp and ustep functions function as before.
Other logical expression capabilities:
Some other logical functions/capabilities that are desirable are:
Type

Possible
Symbol

Provided

Alternate

Comments

IF ..THAN..ELSE expressions  See text  Yes  Two different formats are allowed  See text. The implementations conform to the most common I..T..E.. formats 
Nested I..T..E.. expressions  NA  partial  Only the else condition can be nested.  Other than using an = test, the IF test can be inverted to place the nested condition in the else portion of the expression. (See Figure 8 and Figure 9.) 
Using ustep functions in I..T..E.. expressions  NA  partial  See Figure 10 and Figure 11.)  
Logical operators usable in other than I..T..E.. expressions  NA  (See Figure 12 and Figure 13).  
Parentheses usable in I..T..E.. logical expressions  NA  some 
Table
2
Logical operators and expression usage
Logical Functions:
What is new and very powerful in Version 5 is the incorporation of the logical "IF … THAN …. ELSE …" function into the instruction set.
Recalling
from the previous articles on logical functions, I devised a method
to use
the uramp() and ustep() functions with the nonlinear function generators
to produce logical expressions. As an example, if we wished to create
a function that returned v2(t) when v1(t) was greater than zero,
and v3(t) when it was not, it could be done in a somewhat contorted
manner, using a nonlinear voltage source as:
V = u(v1(t))*(v2(t)  v3(t)) + v3(t)
Recalling, the u() function returns a '1' when the argument is greater than zero, and zero otherwise. Thus, when v1(t) > 0, u(v1(t)) =1 and the equation becomes:
V = 1*(v2(t)  v3(t)) + v3(t) = v2(t)
Whereas, if v1(t) were equal to or less that zero, the result is:
V = 0*(v2(t)  v3(t)) + v3(t) = v3(t)
Now, what Version 5 does is precisely the same thing, but the syntax is cleaned up. Using a different syntax, the same functions have been used to produce the output. A ustep function is still used, but it becomes invisible to the user.
There are actually two different ways the "IF … THAN …. ELSE …" function has been incorporated into the instruction set. The reasons why are for another reason I will not reveal here, but the two means are described in the following.
Method 1:
v = IF ( test, THEN_true_test_output, ELSE_false test output)
The preceding equation should be rather easy to understand. Within the brackets are three items, separated by commas. The first is the actual test expression. IF this expression results in a true value, the second expression is the voltage that 'v' will present as an output. If the test presents a false output, then the third expression is the voltage output. This is best seen by an illustration. Figure 1 following is a small test circuit.
Figure 5
Method 1 test ckt 1
A netlist for the circuit follows:
if_then_else.cp~
***** main circuit
B1 1 0 v = IF ( v(3)<1, 0, 1)
R1 3 4 1K
V1 3 0 SIN( 0.000000000000e+000 5.000000000000e+000 1.000000000000e+006 0.000000000000e+000 0.000000000000e+000)
R2 4 0 1K
R3 1 0 1K
.TRAN 1E11 1E7 0 1E11 uic.end
The leftmost generator V1, is a sine wave source with an amplitude of 5V peak, centered about zero volts. B1 generator is used to create a logical output voltage. The requirement for B1 is that, IF the voltage output of generator V1 is less than one volt, that the B1 output will be zero volts. And if the output of generator V1 is equal to or greater than 1 volt, then the B1 generator will be 1 volt. (Note that the output probe for generator V1 is voltage V2, and the output probe for generator B1 is V3. Whereas in the equation for generator B1, the node voltage at node 3 with respect to node 0 is understood.)
An output graph showing the input voltage v2 and the output voltage v3 is shown in Figure 2 following:
Figure
6
Method 1 test ckt 1 graph
Here we see that when the green input voltage at v2 is less than 1v, the output is zero, and 1 volt otherwise. Now the test was :
B1 1 0 v = IF ( v(3)<1, 0, 1)
This could have been performed in nearly the same manner with a B1 source equation of:
B1 1 0 v = IF ( v(3)>1, 1, 0)
This would for all practical purposes be the same circuit, IF the voltage generator V1 did not dwell at zero. For, the first equation is equivalent to:
B1 1 0 v = IF ( v(3)>=1, 1, 0)
But there is no >= operator, so they are NOT precisely the same even were that operator available.
The point that should be remembered is that for real variables the use of an '=' (or an '==' ) operator for a test, other than was done through inclusion in an else condition by implication, is problematic at best. Remembering that SPICE produces a numerical output, at solution times that might not EVER be precisely right to produce a given value, let alone have two real solution values both meet at the same time, it is best NEVER to use an equality test save for logical values.
Now of course some care must always be used in creating tests, however I believe it is clear that the logical expressions are far, far easier to produce and understand than the ustep method.
The next question that arises is, can these expressions be nested? The answer right now is YES, you can nest these conditions under certain conditions. Refer to Figure 7 following:
Figure
7
If..Than ..Else Method 1 circuit 1
The results indicate that ITE nesting can only occur in the 'else' section of the expression. Here, a first level of nesting works. For reference a 'working' netlist of the circuit of Figure 7 is as follows:
ITEm2 #1.cpr
***** main circuit
V1 1 0 SIN( 0.000000000000e+000 1.000000000000e+000 1.000000000000e+003 0.000000000000e+000 0.000000000000e+000)
V2 2 0 SIN( 0.000000000000e+000 1.000000000000e+000 3.000000000000e+003 0.000000000000e+000 0.000000000000e+000)
V3 3 0 SIN( 0.000000000000e+000 1.000000000000e+000 5.000000000000e+003 0.000000000000e+000 0.000000000000e+000)
V4 4 0 SIN( 0.000000000000e+000 1.000000000000e+000 7.000000000000e+003 0.000000000000e+000 0.000000000000e+000)
R1 1 0 1K
R2 2 0 1K
R3 3 0 1K
R4 4 0 1K
B1 5 0 v = IF (v(1) > v(2),1,0)
B2 6 0 v = IF (v(1) > v(2),v(3),v(4))
B3 7 0 v = IF (v(1) > v(2), 1, IF (v(3) > v(4), v(2),0 ) )
R5 5 0 1K
R6 6 0 1K
R7 7 0 1K
.TRAN 1E6 0.05 0 1E6 uic.OPTIONS method = trap
.end
Notice from the above netlist the v5 output creates logical type outputs (1,0 values), the v6 generator produces real variable outputs, and v7 produces a combination of logical and analog output signals. These are shown in the graph of Figure 8 following:
Figure 8
If..Than ..Else Method 1 circuit 1 test
The question remains, how many nesting levels can one perform? Well, one first question should be, how many does one need, and how many can one conveniently implement and stay sane? IF we could nest loops in the THAN as well as in the ELSE portions of the test, I would say that one level of nesting would be sufficient for most needs, but this is of course just my opinion. With a little work, one can see that one can do two nested THAN's.
The rule is that at least at least three 'than' statements can be in nested IF loops. However, no IF loop resultant seems to be capable of being used as an intermediate product in a more complex expression. That is to say, one could not multiply the result of an IF..THAN..ELSE loop resultant value by another variable.
Method 2:
The second method of creating a logical IF… THEN …. ELSE …. Expression uses the syntax:
v = <exp> ? true : false
Other than the slight format difference, it should be evident that there is very little difference between the two methods. If the reader is interested, one can easily perform the tests on this second method to see what the capabilities and restrictions are.
Summary:
There are now very few features lacking in the enhanced logical equation capability in Version 5.14, and it represents a SIGNIFICANT improvement in the ease of implementation of logical expressions, consistent with that used by competing products in most cases.
However it is not yet fully tested. It may never be. What needs to be done is to create a matrix of operators/functions, and using a binary type process select and test combinations of usage of these items, in varying complexity, to determine the capabilities and limitations under those conditions.
Just such testing and reporting, as is done here, represents important feedback to the B2SPICE programmers. Even with some of the limitations found here, most logical expressions desired can be formulated easily with the existing tools. Moreover, some of the 'limitations' if and when corrected will represent an advance over and above what competing products have.
B2.Spice A/D Logical Expressions: Part 2
Summary: Since the last article pertaining to logical expressions, some changes have occurred. B2SPICE™ version 5.2.2 has added to and improved the logical expression features of v5.1.6 and proceeding dramatically. Boolean logical expressions and operators and logical gate operators and expressions have been revised and expanded and can be used the same time, in combination. Without being formally 'exact' in their description, this article is intended to summarize and explain the features of their implementation within B2SPICE.
Their usage is compatible with the most common usage of these operators in other versions of SPICE, however, their capabilities in other regards, are more general.
What is REALLY new is the ability to use these expressions within and out of ITE expressions, and the mixing of them. This is 'leapfrogging' a step ahead of most competitors. And the older usage of logical expressions with mainly the ustep and uramp operators is unchanged.
While there are a still few problems or perhaps 'druthers' in the implementation, these can be overcome without great difficulty  and the competitors do not have these features. There are now more complexities, however that is a required price for added power they bring to simulations. These changes are significant and part of the evergrowing capabilities of B2SPICE.
Definitions:
In order to be sure that the descriptions of the logical features are clearly conveyed, some definitions and explanations are in order.
There are two basic types of circuit models. They are STRUCTURAL models and BEHAVIORAL models.
Structural models are prepared using the familiar elements such as resistors, capacitors, transistors and other devices that are builtinto the SPICE program. In general structural models allow one to change device parameters, but not the underlying code that determines device operations.
Behavioral models use equations and expressions to produce devices that, at their external terminals, behave similarly to the devices/circuits/functions being modeled. The equations/expressions used in behavioral models can in themselves be behavioral models, and they can involve structural elements.
As one example, a Laplace transform model of an ideal filter is in one sense a behavioral model, and it could be said in another sense to be a structural model, as it is in the standard library. It can be used with other devices/models to create new devices. Other examples will be shown herein where standard 'B' type arbitrary nonlinear sources incorporate equations and expressions that can themselves involve such elements as other voltage sources, resistors and other structural elements. Structural and behavioral device elements and models can be combined and used in more complex higherlevel models.
The equations/expressions used in behavioral models can also be of two types. There are arithmetic expressions which are ordinary mathematical operations using ordinary arithmetic and transcendental functions. There are also logical expressions.
Logical expressions are expressions where the result/outputs are binary in nature, or where a binary computed value could modify or select real outputs. That is to say, the result after evaluation of the expression will be essentially bipolar (or multipolar) in nature, such as one value or another, or one expression result or variable or constant or another. They can and often do have some arithmetic functions/expressions within them.
There can be two different types of logical expressions. A Boolean logical expression or operator results in operations/actions that operate on and/or result in TRUE/FALSE values, however, the analog levels or values interpreted/evaluated/associated with TRUE/FALSE signals will always be one or zero.
An xSpice logical expression or a logical gate expression is similar to the preceding, however the analog levels or values interpreted/evaluated/associated with TRUE/FALSE signals may differ. The logic and levels used in valuation of these operations will be in general accordance with the Boolean algebraic logic rules and the xSpice parameter settings. Logical gate expressions produce outputs that can be identical to or similar to xSpice digital elements. The subject of logical expressions, and logical gate expressions/operators will be discussed in more detail later.
An InLine Equation can contain of either or both of the two logical expression types and more, however, the means of using these logical expression types and their results when used within an IF…THEN …ELSE (ITE) or an IF … THEN (IT) construct or function can be different than using them otherwise. Generally gate logic operators are not usable within ITE or IT constructs without some care, but it is possible to mix them.
Analog signals cannot directly drive xSpice digital devices, nor can xSpice digital device outputs directly drive analog devices. The representations of these devices and the values they produce/require is different. An xSpice digital signal has just three input and output values, one, zero or '?'. (Which is why I said they GENERALLY follow the Boolean logical rules.)
SPICE3.x with xSpice has special BRIDGE devices that convert these signals automatically from one type (including several others not mentioned) to the other as required or specified. The '?' output is a digital indeterminate output which can indicate that the digital output cannot be definitely assigned a ONE or ZERO logic level in accordance with the xSpice function or bridge device rules. It usually is translated as a value of half way between the true and false levels.
Unseen in most cases is the 'bridge' device, which converts an analog signal into an xSpice digital format, and another 'bridge' device that does the converse, although explicit models do exist in the library that may be used when necessary. For example, a signal that is created using xSpice compatible voltage levels as a 'B' element output needs to be converted into an xSpice logical output to drive the library xSpice digital devices.
Bridge devices are generally required to convert logical gate output values into analog signals. They are NOT required to convert Boolean logical values into analog signal levels, as these are a special class of values.
Now using digital values in an analog 'B' device converts them into an analog form at their output. This is done implicitly within the B device. Whether the B device output represents a Boolean logical output, a gate logical element or an analog output is something the user must determine through construction. No matter what, the output will always be treated as an analog value. This may be seen in a graph of the outputs. 'B' device outputs will be grouped with analog signals.
Logical Gate Expression Primitives:
Pertinent excerpts from the B2SPICE™ provided guide to using logical expressions and operators, written for version 5.1.6, follow:
NonLinear Controlled Sources (extension):
Names: arbitrary voltage source, arbitrary current source
category: virtual: voltage sources and virtual: current sources
We have implemented If then else expressions and direct digital and logical expressions.
Here are some examples:
B1 nplus nminus V = if(v(2) > v(1), 5, 0) // comparator, pspice syntax
B2 nplus nminus V = v(2) > v(1) ? 5 : 0 // comparator, ISspice syntax
B3 nplus nminus V = !(v(2) & v(1)) // nand gate
B4 nplus nminus V = (v(2) > v(1)) \ (v(2) > v(3)) // '\' is the logical or.These types of expressions can be used for sophisticated modeling within your circuits. I've included more details on these expressions and operators at the end of this article.
More notes on IfThenElse (ITE) expressions
Within the ITE condition, change nothing... except fix up operator precedence bug, and add exclusiveor.
Logical operators supported:
&: and
: or
#: xor
!, ~, ': notComparison operators:
>, <, = for greater than, less than, and equal.
These ITE expressions can be nested, e.g.
If((v(1) > v(2)) & (v(1) > v(3)), v(1), if(v(2) > v(3), v(2), v(3))) // pspice syntax
((v(1) > v(2)) & (v(1) > v(3))) ? v(1) : (v(2) > v(3)) ? v(2) : v(3))) // isspice syntax
Will return the maximum of v(1), v(2), and v(3)More notes on logical and digital expressions outside of the ITE
Comparison operators: >, <, =.
These take real inputs and generate logical (0,1) outputs.Digital operators:
&: and
: or
#: xor
!, ~: notThese take real analog inputs, convert them to digital signals and perform the operation, then convert the outputs back to analog again. The conversions from digital to analog, and back from digital to analog, use the parameters in the digital simulation options (bb_ad* and bb_da*) for threshold levels and for high and low voltages.
e.g. v(1) & v(2) // will return 5V (bb_daOutHigh) if both v(1) and v(2) are greater than 2.5V (bb_adInHigh), else return 0 (bb_daOutLow).Logical operators: (THIS IS NEW)
These take logical inputs (0,1) and generate logical outputs (0,1).
' : invert (this is the apostrophe that's with the quotation mark)
$ : and
\ : or (backslash, not division symbol)
@ : exclusiveore.g. (v(1) > 0) $ (v(2) > 0) // will return 1 if both v(1) and v(2) are greater than 0, else return 0.
In this article we shall be exploring and examining the latest capabilities of B2SPICETM as described and explained in the listed excerpts.
NonLinear Controlled Sources (extension):
The general expressions and their format are unchanged. The description shows that, within a 'B' element, that ITE expressions and logical expressions can be used. What is not explained are the limitations on their use. For example, at this time, an ITE expression must be standalone. Meaning that an ITE expression cannot be used in one 'B' type element where the resulting values are used as part of another expression, nor can two different ITE expressions used at the same time. In other words, an expression such as:
v = if((a>b),c, d) + If((e>f),g,h) (eq. 1)
or
v = x^(if((a>b),c, d)) (eq. 2)
are invalid. ('a' through 'g' are expressions equations, functions or constants.) This is not compatible in some respects with other versions of SPICE. Especially with some constructions in the form of equation 2. It would be most useful if an ITE expression result were treated as an ordinary variable or expression result, with a numeric result after the expression was evaluated placed on a results stack, such that it could be used with other functions and expression results within the same equation.
Now for logical expressions there is the same question as two limitations. For example, would an expression such as:
V =! (v(2) & v(1))*v(3) (esq. 3)
be allowed? A simple circuit with simple sine wave voltage sources
v1 through v4 and B1 through B3 generators was created for test
purposes. The sine wave sources were 5.0V each, and the v1 through
v4 frequencies were 1k,3k,5k and 7kHz respectively. The circuit
is shown in Figure 1 following:
Figure 1
Test circuit
A graph of the simulation output is shown in Figure 2.
Figure 2
Test circuit graph#1
Trace v5 is that of the equation 3, in green. Trace v6 in red is just the logical gate portion of equation 3, and trace v7 is v(3). Remember that is a logical gate implementation. Thus v6 is a logical gate expression. It happens that the logical gate output high level is 4.0V, and the logical gate output low level is 0.3V.
Thus, because of the construction of the equations (no comparison elements were used), it is interpreted as a logical gate expression and v(3) is multiplied by the logical gate output high and low levels at the appropriate times.
Now the question arises, what happens if this logical gate expression is inserted into an ITE expression, such as perhaps:
v = !(v(2) & v(1)) ? !(v(2) & v(1)) *v(3) : !(v(2) & v(1)) *v(3) (eq. 4)
Here we have recreated the operations of the test circuit #1 with the B1 equation as shown in equation 4. The test produces logical gate voltages, and these voltages as before multiply v(3). The result is identical. We can insert logical gate expressions within ITE expressions, and with the proper construction do the same operation, although it is a little bit wasteful to do so as equation 3 is more succinct than equation 4.
Now IF the term '!(v(2) & v(1)) *' had been omitted from the THEN and the ELSE result changed to 0, then the results would just be the selection of the THEN or the ELSE results dependent on the logical gate expression being true of false.
The key thing to remember that if all the individual terms comprising the IF test condition involve comparisons or equality, then the resultant of the test condition are Boolean logical outputs. Otherwise they are interpreted as being logical gate outputs. Now because the threshold levels differ, if real variables are converted to Boolean logical values in a test as opposed to using logical gate operators, the results may differ with differing thresholds.
The question that remains is whether the logical gate values are accessible within the 'B' element as constants. To determine this, we will include the indeterminate input threshold level value of bb_daOutX as a comparison. That is, wherever there is a v(1) or v(2) in the expression of equation 4, it will be replaced by the term '(v(1) > bb_daOutX)' and '(v(2) > bb_daOutX)'. Doing this and repeating the simulation produces an error. These values are not accessible to the user. It would be nice if they were, as if the current simulation temperature and/or some other simulation variables were also available, one might be able to dynamically vary subsequent simulation passes.
Comparison operators:
The comparison operators listed all produce Boolean logical outputs from their operands, within or without of ITE expressions.
Digital/logical operators:
There are 4 digital operators and 4 logical operators defined, what I would call logical gate operators and Boolean logical operators, the AND, OR, EXCLUSIVE OR and Not(invert). See Table 1.
Function

Logical
gate

Boolean
logical

AND

$

&

OR

\



XOR

@

#

NOT

'

! or ~

Table
1
Digital/logical operators
The question arises, what happens with these operators when used outside of their 'class'? There are two general facets to this question. What happens when a logical gate operator is used with a Boolean logical variable (or an expression that returns a Boolean logical result), and when a Boolean logical operator is used on a logical gate variable (or an expression that returns a logical gate result)?
A Boolean expression normally returns two resultant levels, one and zero. Dependent on the values of the SPICE constants governing the various logical gate expressions, it is possible that one could define them such that the result would be correct. However, were there any other logical gate devices present, these could be adversely affected. Normally this would result in a static zero resultant however.
A logical gate expression normally produces two or three positive levels. A Boolean logical operator would interpret these all as a nonzero value of logic one.
NOTE: Notice that what is being discussed is unary operators that have a single operand, the value returned by an expression.
It is entirely possible for these operations to occur properly in the case of Boolean logical expressions (with comparisons) using logical gate operands, and in the case of logical gate expressions using Boolean logical expressions as operands IF the threshold levels are properly applied.
What is recommended that for sanity sake one not mix the two unless one is sure of what one is doing, and there is no possibility that modification of logical gate values (if done) would cause a circuit or device one creates to fail to simulate properly if other logical gate devices are subsequently used in the design.
For example, IBIS type parts usually use the same digital simulation parameters as do Xspice devices. Now we do not yet have an IBIS capability, but we doubtless soon will. Plan ahead.
Conclusions:
The
logical expression and operator capabilities of B2SPICETM are now
just about as rich or richer than any other SPICE implementation
I am aware of. This gives the analyst an extensive set of tools
to use in creating behavioral, logical expressions for use in circuits
and parts.
B2.Spice A/D Logical Expressions: Part 3
Summary:
B2SPICE version 5.2.3 has added to/improved the logical expression
features of v5.2.2 and preceding. For the first time, and what seems
to be unique to B2SPICETM, ITE expressions are treated as functions/operators
that return a value. Thus, within a arbitrary nonlinear source or
'B' generator, two or more of these expressions may be used within
a single equation and/or combined with other mathematical operations.
In certain cases this may the use of fewer 'B' type elements within
a realization and a simplification and more concise circuit representation
to occur. Without being formally 'exact' in their description, this
article is intended to summarize and explain the features of their
implementation within B2SPICE.
Enhanced Boolean Logical expressions:
It is assumed the reader has struggled through the previous two logical expression articles with some measure of success. Please read them if this is not so.
The previous articles showed how one could construct and utilize ITE expressions in the pseudo code form of:
v = If A then B else C eq.1
to form useful expressions. But now, the expression has been revised to where it can be treated as an operator/function returning a value, and thus expressions in the form of:
v = (If A then B else C) * (If D then E else F) eq.2
or
v = (If A then B else C) * G eq.3
are valid. Now the elements A through G may be valid constants, voltages or currents, or combinations of expressions which could in themselves include ITE expressions, logical expressions, logical gate expressions or other valid constructs.
Were 'G' a constant or a simple variable, equation 3 might be simplified to where the 'then' condition was B*G and the 'else' condition was C*G, certainly so if G was simple, but were 'G' a complex expression and neither 'A' nor 'B' zero, separating it out might make sense. There would then only one 'G' expression to create and debug.
Now
majority logic is a way of implementing digital operations based
on the principle of majority decision. The logic element, a majority
gate, has an odd number of binary inputs and a binary output; the
gate symbol and logic operation for a threeinput majority gate
are shown in Fig. 1. The output is a logical 1 when the majority
of the inputs is logical 1 and a logical 0 when the majority of
inputs is logical 0. Any digital function can be
implemented by a combination of majority gates and binary inverters.
Majority logic provides a concise implementation of most digital
functions encountered in logicdesign applications.
Let us consider a 3 input majority gate, with inputs 'A', 'B' and 'C'. The output should be true if any two inputs are true. The pseudo equations describing this are:
V = If ((A and B) or (B and C) or (A and C)) then 1 else zero. eq.4
So far, that is easily performed using the version 5.2.2 logic capabilities. This could be implemented, assuming that the inputs were logical voltages levels v(a), v(b) and v(c), in a 'B' element as:
V = ((v(a) @ v(b))  (v(b) @ v(c))  (v(a) @ v(c)))?1:0 eq.5
Now suppose that there was another input, an 'inhibit' input v(d), that would prevent a true or logic one level output when it was true. This could result in an expression such as:
V = ((v(a) @ v(b))  (v(b) @ v(c))  (v(a) @ v(c)))*!v(d)?1:0 eq.6
Even with simple expressions it is easy to see how the situation can become more complicated rather quickly. An alternate expression that might make more sense could be:
V =( !(v(d)))*( ((v(a) @ v(b))  (v(b) @ v(c))  (v(a) @ v(c)))?1:0) eq.7
An alternate expression is:
V =( ((v(a) @ v(b))  (v(b) @ v(c))  (v(a) @ v(c)))?1:0) * (!v(d)?1) eq.8
A circuit to test this was constructed as shown in Figure 1 following:
Figure 1
Test circuit 1
In this circuit the equations in the B1, B2 and B3 sources were those shown in equations 6, 7 and 8 respectively. A graph of this circuit is shown in Figure 2 following:
Figure2
Test circuit 1 graph
In Figure 2 it can be seen that the outputs are inhibited when v8, the inhibit signal, is true. The first two equations have the inhibit signal embedded within the ITE expression, while the third represents the output as the product of two ITE expressions, showing that they do indeed may be treated as separate functions returning values in more complex expressions.
The main utility of this capability is in the easing of the creation of complex expressions, sometimes eliminating one or more 'B' devices, enabling 'factoring' to remove common terms in result expressions, as well as minimizing the need to create nested ITE functions more than two levels deep to product such functions as a multioutput branch function.
Like many good things, this capability comes at a price. Namely, that one must pay more attention to the grouping of terms using parentheses. Consider an expression of the form:
V = A>B? C: D +E eq.9
This will be interpreted to produce an output of either C+E, or D+E as an output. If the desired result is C or D+E, the D+E term needs to be enclosed within parentheses.
Conclusions:
Several times in the past I have wished I could use multiple ITE expressions within a 'B' element, or to use the returned values in another expression. While not earthshaking in its implications, another interesting capability has been added to the B2SPICETM toolbox. It keeps getting better and better.