Logical Expressions - NO Smooth Switch #2

About the writer: Harvey Morehouse is a contractor/consultant with many years of experience using circuit analysis programs. His primary activities are in Reliability, Safety, Testability and Circuit Analysis. He may be reached at harvey.annie@verizon.net. Simple questions for which I know the answer are free. Complex questions, especially where I am ignorant of the answers, are costly!!!

Summary: In this article I describe now to make a smooth switch model, Smooth Transition Switch Type 2 (STSNOT2).

Smooth Switches:

In the previous article a rather lengthy discourse was provided. It is assumed that the reader is familiar with that article hence this article will be much briefer, as the model is similar as are the test circuits. Here an exponential approximation is used to vary the switch model 'resistance' within the switching range.

Because of this, even when 'ON' and 'OFF' points are set for input voltage levels where the switch is fully on, and fully off, the switch will not usually show large changes at these levels. However they define the region where the transitions will occur as being somewhere within those levels, depending on definition as well as the shape of the input waveform and the nature of the external circuitry as well.

STSNOT1:

This switch model which smoothly switches is shown in Figure 1 following:

Figure 1
STSNOT1 switch model

This model is very simple. A control voltage is applied between N3 and N4 terminals, and the switch contacts are represented by the circuitry between nodes N3 and N4. Generator B1 applies a current between nodes N1 and N2, which is dependent on the voltage between nodes N3 and N4, as well as the voltage between nodes N1 and N2.

Specifically, for the B1 source, its current value is set as:

i = (1-u(v(N3,N4) -1))*v(N1,N2)/1e6 + u(v(n3,n4)-4)*v(N1,N2)/.1 +
(1-u(v(N3,N4)-4))*u(v(N3,N4)-1)*V(n1,N2)/(EXP(LN(((.1*1e6)^.5)) +
3 * LN((.1/1e6)) * (V(n3,n4) - ((4+1)/2)) / ((2* (4-1))) -
2 * LN((.1/1e6)) * (V(n3,n4) - ((4+1)/2))^3 / ((4-1)^3)))

This equation was taken from reference 1, with some slight modifications. The equation covers three regions of operation. Later, this will become a parameterized equation (as per reference 1) however we wish to test it first and explore its operation. Consequently, Ron is represented by a value of 0.1 ohms, Roff by 1e6 ohms, Von by 4 volts, and Voff by 1 volts. Von should be greater than Voff.

The first region is where the input control voltage is equal to or less than Voff, and is comprised of the term:

(1-u(v(N3,N4) -1))*v(N1,N2)/1e6

Here the portion u(v(N3,N4) -1) tests to see if the input control voltage is greater than Voff. (Please refer to the 'logic' articles at the B2SPICE web page under RESOURCES if this is not clear.) This function will return a value of 1 if the condition is true, and zero if it is false. Subtracting this value from unity will produce a function that will be true IF the control voltage is NOT greater than Voff. In that event, the current through terminals N1 and N2 will be equal to the voltage across terminals N1 and N2 divided by Roff

The second region is described by the term u(v(n3,n4)-4)*v(N1,N2)/.1. Here the test performed by term u(v(n3,n4)-4) determines if the control voltage is greater than Von, and if so, the current through terminals N1 and N2 is set by the voltage across those terminals divided by Ron.

The third region is intermediate between those regions, where the control voltage is greater than Voff, but less than or equal to Von. The region is defined by the term (1-u(v(N3,N4)-4))*u(v(N3,N4)-1). In that case the current through terminals N1 and N2 is set as the voltage across those terminals divided by a resistance defined by the remainder of the equation.

A test model of this circuit is shown in Figure 2 following:

Figure 2
STSNOT2 test circuit #1

The test circuit is quite straightforward, however translating and typing the equation into a working form was a chore. To simplify the operation, sources B4, B5 and B2 were used to simplify the typing and keeping track of the brackets. They represent the three regions of operation previously described. Initially the value for B1 current was set to be I = v(7) + v(14) + v(12) until debugging was completed, whereas in the final form the terms were directly entered into B1 source. The final model includes only the B1 source.

(An astute reader might notice the presence of sources V3 and V4 and wonder what purpose they serve. What they do is to isolate the nodes N4 and N2 from ground, allowing the equations used in the circuit to remain without renaming them to node 0. The sources are zero volts, similar to the ammeter model, which isolate nodes while allowing them to be electrically identical. This technique is also usable in creating a chip model where several instances of a circuit point are brought out to two or more external pins. Now one could use a very small resistance to the same effect, but this is more elegant.)

B2 was a test source used to examine some of the individual logic operations used in B3, B4 and B5 models during realization of the model. V1 is a pulsed 5V source, 50% duty cycle, with a 1p sec rise and fall time and a period of 0.02u sec. This voltage is integrated by R5 and C1 to form a smooth ramp. Again this is not realistic to drive a 'real' mechanical switch or even to simulate most transistors, but it illustrates the action of the switch, which is shown in Figure 3 following:

Figure 3
STSNOT2 test circuit fall time graph

The yellow trace shows a smooth transition of voltage across the switch, the N3 terminal voltage.

The switch itself needs some more testing. The most important case (for me) is where the switch is driving a capacitive load, and where the load capacitance behaves as an infinite capacitor over a range. This is the case for a real diode and a good model, where it takes time to switch the diode from a conducting state to a non-conducting state. During the reverse recovery time it presents an essentially constant 'ON' voltage until the excess charges are swept out of the device. This application is perhaps best tested in the case of a simple model of a BUCK converter. A test circuit is shown in Figure 4 following:

Figure 4
STSNOT2 test2 circuit 2

In this circuit the switch represents a switching transistor in a BUCK converter model. The BUCK converter itself is shown as open loop, to simplify the test circuit. A small portion of the output is shown in Figure 5 following:

Figure 5
STSNOT1 test2 circuit2 graph

Here we can see the expected sawtooth current in the inductor after all of the transients are essentially over. There is a small current spike through the v2 source when the switch turns on, which is to be expected (the orange trace).

As you will see if you make the models (or they are included in the library) and perform the simulations, they take a long time to simulate. And however much time it takes for the open loop buck converter we have used here to simulate, addition of a controller chip with a modulator, error amplifier, comparator and other circuitry could add considerably to the simulation time. Using other than behavioral devices would take even longer. It is important to use the fastest computer possible with lots of memory for SMPS simulations. This model will be converted into a parameterized subcircuit part, and hopefully will be added to the B2SPICE standard library.

NOTE: Occasionally in using this model one will see exponent error notations, where an exponent is to large to be resolved. This occurs because the logical functions as implemented in B2SPICE are not true IF… THEN …. ELSE functions, in that all of the terms will be resolved and calculated. Unlike such a function written in 'C' code, where if specified else conditions are met, the remaining ELSE functions are ignored, they are resolved here. However, these conditions are in the denominator of a function, and result in a '0' (or nearly so) final calculation. Consequently these conditions may be safely ignored, as they will not affect the final calculations.

Conclusions:

A smooth switch model was created which can be used in simulations in place of transistors or abruptly varying switches to ease simulation times and aid in circuit convergence. The use of this model within a primitive Buck switching circuit is shown.

References:

1: PCBCafe.com Online Book. http://www10.pcbcafe.com/book/parse_book.php?article=SMPS%2F51intro.htm