Basic Logic Devices:

The basic logic devices to be parameterized are shown in Figure 1 following:

Figure 1
Basic logic gates

Version 5 models:

AND2:

The AND2 device model is shown in Figure 2:

Figure 2
V5 AND2 Circuit

The parameterized equation for B1 generator in what will become the AND2 device is shown in Figure 1, together with the parameters to be passed and their default values. A test circuit is shown in Figure 3.

Figure 3
V5 AND2 test Circuit

Here we are stimulating the circuit with two pulsed voltage sources, each of which having an RC circuit load to simulate the output of a gate of some sorts. A graph of the circuit outputs is shown in Figure 4 following:

Figure 4
V5 AND2 test Circuit graph

There are no surprises in this circuit. All works as expected. There ARE some 'slivers' in the outputs, but this is to be expected, as the inputs will occasionally be such to produce them.

AND3:

The AND3 circuit is very similar to the AND2 circuit, with just another term added to account for the third input. The circuit is shown in Figure 5 following:

Figure 5
V5 AND3 Circuit

The AND3 test circuit is again similar to that of the AND2 circuit, and is shown in Figure 6 following:

Figure 6
V5 AND3 test Circuit

A graph of this circuit output is shown in Figure 7 following:

Figure 7
V5 AND3 test circuit graph

Here we see the expected results. The generator periods were chosen deliberately to create all possible combinations of input signals, and naturally enough there are again some slivers. However, expanding the graph shows that the slivers are appropriate for the input signal conditions.

NAND2:

A NAND gate is a simple variation of an AND gate, with the THEN and the ELSE conditions transposed. This is shown in Figure 8 following:

Figure 8
V5 NAND2 Circuit

The test circuit for this device is shown in Figure 9 following:

Figure 9
V5 NAND2 test circuit

A graph of the circuit output is shown in Figure 10 following:

Figure 10
V5 NAND2 test circuit graph

The NAND2 device works as expected. When both inputs are HIGH, the output is low.

NAND3:

The NAND3 device is just a variation on the AND3 device. The NAND3 model is shown in Figure 11 following:

Figure 11
V5 NAND3 circuit

The test circuit for this device is that for the AND3 circuit, with the exchange of the VOl and VOh terms in the B1 generator.

Figure 12
V5 NAND3 test circuit

The graph of the circuit output is shown in Figure 13 following:

Figure 13
V5 NAND3 test circuit graph

Here we see the NAND3 circuit is well behaved.

OR2:

An OR2 circuit is shown in Figure 14 following:

Figure 14
V5 OR2 circuit

A test circuit for this device is shown in Figure 15 following:

Figure 15
V5 OR2 test circuit

A graph of this circuit output is shown in Figure 16 following:

Figure 16
V5 OR2 test circuit graph

Again the circuit behaves nicely.

OR3:

An OR3 device was not provided for version 4, but for completeness, it is included here. The circuit is as shown in Figure 17 following:

Figure 17
V5 OR3 circuit

The OR3 test circuit is shown in Figure 18 following:

Figure 18
V5 OR3 test circuit

The graph of this circuit is shown in Figure 19 following:

Figure 19
V5 OR3 test circuit graph

NOR2:

The NOR2 circuit is shown in Figure 20 following:

Figure 20
V5 NOR2 circuit

The NOR2 test circuit is shown in Figure 21 following:

Figure 21
V5 NOR2 test circuit

A graph of the test circuit output is shown in Figure 22 following:

Figure 22
V5 NOR2 test circuit graph

NOR3:

The NOR3 circuit is shown in Figure 23 following:

Figure 23
V5 NOR3 circuit

The test circuit for this device is shown in Figure 24 following:

Figure 24
V5 NOR3 test circuit

The graph for this circuit is shown in Figure 25 following:

Figure 25
V5 NOR3 test circuit graph

INV:

An inverter circuit is shown in Figure 26 following:

Figure 26
V5 INV circuit

A test circuit for this device is shown in Figure 27 following:

Figure 27
V5 INV test circuit

The graph of this device is shown in Figure 28 following:

Figure 28
V5 INV test circuit graph

These devices have been tested previously and they work as expected. Consequently no tests will be performed here.

Summary:

A set of parameterized devices has been created for two and three input AND, NAND, OR, NOR devices and an inverter using just a small portion of the logical expression capabilities of version 5.15+. For those persons who have followed the logical expression articles, which in the main have been based on use of the ustep and uramp functions, it should be clear how much easier it is to create and understand devices implemented with these functions. These devices will be incorporated into the version 5 standard library, and should be available at the next program update following the appearance of this article on the B2SPICE web site.