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Logical Functions - CorrectionsAbout the writer: Harvey Morehouse is a contractor/consultant with many years of experience using circuit analysis programs. His primary activities are in Reliability, Safety, Testability and Circuit Analysis. He may be reached at harvey.annie@verizon.net. Simple questions for which I know the answer are free. Complex questions, especially where I am ignorant of the answers, are costly!!! Summary: In previous article I showed how to create logical expressions. While largely correct, there were some misleading statements and errors in the article. In order to correct these items, this short correction is provided. Nonlinear Source 'u' element: Contrary to what was written and implied, THERE IS NO AMBIGUITY IN THE OUTPUT OF THE U ELEMENT. For a given f(v,Z,t), the output of a u(f(v,Z,t)) operation will return an output which is unity when the argument is greater than zero, and zero otherwise. This may be seen from examination of the test circuit of part 1 of this article. There may be a seeming ambiguity in some logical operations using 'u' expressions. If two or more 'u' expressions are summed, the output is NOT a logical OR of the two 'u' expressions but an arithmetic sum of the values of the 'u' expressions. Consequently, given functions f(a), f(b), .f(z) where it is desired to get an output when any of these functions are greater than zero, it must be recognized that in this case one might get 26 different levels from the sum of the 'u' values for each expression.. Each non-zero level could represent different combinations of individual 'u' expressions. Consequently, in every case where 'u' expressions are summed to get a logical 'OR' output, an outer 'u' of this sum must be performed in order to get a unity multiplier for some output value. Where
'u' expressions are multiplied, any single zero 'u' expression over
an interval will 'blank' the overall product during that interval,
and the overall product will be unity or zero, consequently a product
of individual 'u' expressions (where these inner products are themselves
corrected if they are the result sums of 'u' expressions) will be
correct. An Aside: This correction became apparent when I was looking into the possibility of incorporating majority logic expressions into a simulation. Basically majority logic assigns differing logical 'weights' to differing gate inputs. When a majority 'weight' is present the gate will switch. This was implemented by a simple sum of 'u' expressions which each were multiplied the appropriate 'weight'. The sum of these expressions was compared to a majority value in an outer 'u' sum of the individual terms.
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