In line with previous definitions, a 'perfect' diode is one whose forward voltage drop is zero volts (or essentially so), and its current in the reverse direction, when the device has an impressed positive voltage from cathode to anode is essentially zero. It has no reverse breakdown voltage, no junction capacitance, storage time effects nor other parasitics. Its resistance in the conducting region is essentially zero.

An 'ideal' diode, on the other, hand, has a non-zero forward voltage drop where conduction begins when it is forward biased at greater than this level, as well as a breakdown voltage level where conduction occurs in the 'reverse' direction when it is reverse biased. In both cases, once the conduction level is reached, essentially no additional incremental voltage drop (due to resistance or other effects) occurs. Again, no junction capacitance, storage time effects nor other parasitics are present, but these effects could be added using additional external circuit elements.

Nonlinear Source 'uramp' element:

The preceding article in this series describes the 'uramp' function in some detail, and will not be repeated other than the definition:

Infinite Impedance:

An infinite impedance (or infinite incremental impedance) condition between two nodes need not occur due to the presence of an impedance whose magnitude is unbounded (or essentially so), although it could. An infinite impedance, in effect, can occur between two nodes over a region where no current flows in response to an externally applied voltage to those nodes. This can occur if there is a voltage internal to the branch which is equal to, and in the opposite sense to, the externally applied voltage. The voltages cancel, and no current flows under those conditions.

Zero Impedance:

A zero impedance (or zero incremental impedance) state exists (under those conditions) wherein the voltage across two nodes is unchanging in response to externally applied current increment through those two nodes. This could occur when the impedance between two nodes is zero, or essentially so, but also where the current(s) incident to a node is (are) exactly matched by a current generator shunting the incident current(s) directly from one node to the other.

Ideal Diode Model:

The perfect diode model must have the following characteristics:

   1. It is a two-port device (at least external to the model/subcircuit for the device).

   2. When the externally applied voltage from Cathode to Anode terminals is negative, essentially no internal current must flow (subject of course to numerical error limit considerations).

   3. When condition 2. is not met, the device current (and voltage) must be determined by the external circuitry, the device behaving as a short circuit (subject of course to the same numerical error limit considerations).

Using an internal opposing voltage source, one can construct a model and a test circuit for the first pass at an ideal diode as shown in Figure 1 following:

Figure 1
Ideal Diode Test circuit

A netlist for the circuit follows:

Performing a transient analysis on the circuit produces the results in Figure 2. The results are as expected, with the simulated ideal diode consisting of the 'B1' and 'R2' elements, having its anode at node 'N1" and its cathode at node '3'.

Figure 2
Ideal Diode test circuit

The operation of the diode circuit is straightforward. The applied voltage is opposed by the 'B1' voltage generator. The voltage of the 'B1' generator is the resultant of two levels. The first part is the absolute value of the voltage from node 'N1' to ground. The second is the uramp value of the voltage from node 'N1' to ground. The uramp value is the value of the 'N1' voltage when it is greater than zero.

Thus, during the half-sinusoid interval when the applied voltage is (or would be) positive, the voltage is unopposed. The equivalent diode 'conducts' with an 'ON' resistance equal to that of R2. During the second, negative half of the rectified sinusoid, the voltage generator 'B1' causes the voltage at 'N1' to be opposed by an essentially equal level, resulting in no appreciable current flow. This is of course an open circuit.

Note that the currents indicated by the ammeter and by the 'B1' source value are 180 degrees out of phase. This is caused by the sense of the 'B1' generator in the circuit. For a voltage source, within that source, 'positive' conventional current flows from negative to positive levels. So far so good, however the sense of the 'B1' generator is negative when it is (for all essential purposes) non-zero. This causes the 'B1' current to seem to be wrong. However as this will be external to the diode model/subcircuit it is of no consequence.

This ideal diode could be added to the library as a device, perhaps as a symbol of a normal diode with a letter 'I' beside it to denote it as an ideal diode. This is left as an exercise for the reader.

This device can be associated with series resistance, parallel resistance and or capacitance as needed to make it somewhat less ideal and ease simulation difficulties at the transition points from conduction to non-conduction and the converse.

Perfect Diode Model:

The perfect diode model would seem to be very similar to that of the ideal diode. The differences are that it should exhibit a forward voltage drop VF when it conducts with an essentially zero incremental resistance state, and when reverse biased with a sufficiently large voltage, it will conduct at a voltage VR with an essentially zero incremental resistance state. At first glance, it would appear that one could use one ideal diode with a fixed voltage source of VF in series opposition to the forward voltage, together with an anti-parallel ideal diode with a fixed voltage source of VR in series with it in its 'forward' direction. The first diode would produce the 'ON' voltage drop of VF when its net applied voltage, Vin-VF was greater than zero. In the reverse direction, the anti-parallel diode would conduct when the overall diode voltage was less than VR.

But, it does not work. The forward characteristics can be simulated by adding a fixed voltage in series with an ideal diode, as can the reverse characteristics by a single anti-parallel diode with an associated VR. But combining the two will not work. A schematic of this failed attempt to create a (partial) perfect diode in that manner is shown in Figure 3 following.

Figure 3
Perfect diode fwd conduction element

The netlist for this circuit is as follows:

Device D1 is a subcircuit representation of the ideal diode. VF is the forward drop of the simulated perfect diode, set at 0.7V. This illustrates the forward voltage conduction portion of the perfect diode and it works as expected. Figure 4 shows the graph of this circuit, with the forward current through the device as the current through voltage source VF.

Figure 4
Forward Conduction of perfect diode

So far, so good. The reader can verify that the breakdown characteristics can be modeled by a reversed D1 and VF (becoming VR). The problem comes when one tries to parallel these items. The circuit, as shown in Figure 5, does not work properly.

Figure 5
(FAILED) perfect diode model

The circuit will not converge. Why not?

There are TWO reasons for this circuit failure. The first is due to the mixing of essentially ideal branches 3-5-0 and 3-6-0. The second is due to the improper modeling of the perfect diode itself.

Considering the first error, it must be remembered that IF a circuit element passes no current, either it has no net voltage impressed, or it has an essentially infinite impedance. In this case, when diode D1 is NOT forward biased, and the anti-parallel diode is NOT forward biased (the overall perfect diode is not conducting), the voltage at node 3 cannot be determined. It cannot simultaneously be both VIN - VF, and VIN +VR or any combination thereof, as D1 and D2 are essentially open circuited.

Considering the second error, the model we assumed without thought, was wrong. There are THREE states of interest for the perfect diode. The ideal diode has only two states. The three states for the perfect diode are as follows:

    State 1: When the perfect diode has an impressed voltage greater than VF, from cathode to anode, it enters a state wherein its terminal voltage is equal to VF from cathode to anode, and the current through the device is (essentially) bounded only by external circuit elements

    State 2: When the perfect diode has an impressed voltage less than VR, from cathode to anode, it enters a state wherein its terminal voltage is equal to VR from cathode to anode, and the current through the device is (essentially) bounded only by external circuit elements

    State 3: When the perfect diode has an impressed voltage less than VF but greater than VR, its terminal voltage shall be that of the impressed voltage (the current is essentially zero)

Another way of looking at the error is that, in the 'B' element equations, the 'scope' of the VF and VR elements, whether added directly to the 'B' element equations or explicitly added as a series generator component, may be universal across all of the states. When using logical expressions we must be careful to ensure that all of the device states are limited properly in scope.

Logically, we need to implement a voltage generator 'B' element expression which has the following effect:

There was a specific reason for writing the region II conditions as shown. Remember that the 'u' function returns a unity value when its argument is GREATER than zero. As mentioned in a previous article, the logical inverse of this condition is a function with a value of unity when its argument is EQUAL TO or LESS THAN zero. Practically speaking, in many cases one could merely invert the original argument to arrive at this, however it is easier to visualize and always correct to create a logical inverse function. Recalling what was previously discussed, if a function exists f(v,I,z,t) such that for v = u(f(v,I,z,t)), v = 1 when the function is greater than zero. Using this level as a 'logical' voltage, its 'logical' inverse is v = 1- u(f(v,I,z,t)), which is unity when the 'u' argument is NOT greater than zero.

The expression for the 'B' generator could then be expressed as:

V = u(v(n1,0)-VF)*VF +
(1 - u(-VR-v(n1,0)))* (1- u(v(n1,0)-VF))*v(n1,0) +
u(-VR-v(n1,0))*-VR

The first line is the region 1 condition. If v(n1,0), the input voltage, is greater than VF, the device is conducting with a voltage drop of VF from anode to cathode.

The second line is the region 2 condition. In this case if the input level is NOT more negative than -VR (the breakdown voltage is specified as a positive level) AND simultaneously, VIN is NOT more positive than VF (the input level is less than VF) THEN the voltage is equal to v(n1,0), the input voltage. The device is essentially non-conducting in this region.

The third line is the region 3 condition. If the input voltage is more negative than -VR (making the 'u' function argument positive), then the terminal voltage is equal to -VR. The device is conducting in the reverse, breakdown region with a voltage drop of -VR from anode to cathode..

A test circuit incorporating this 3 region model with some modification is shown in Figure 6 following: The difference in this modified test circuit is that the three regions are separately modeled with individual generators for each region, and no modifying voltage terms for the three regions. The purpose of this test circuit is to ensure that the each individual modifier covers the appropriate region, and sum of all three of the modifiers is unity, showing that all regions are accounted for in the three terms. VIN is set to 10 VAC, VF is set to 2 volts (to accentuate the conduction region) and VR is set to 8 volts.

Figure 6
Perfect diode region test circuit

The netlist for this circuit is as follows:

In this circuit generator B1 (voltage v(n3)) produces the multiplier for the VF term, region 1, B3 (voltage v(n5)) produces the multiplier for the VR term, region 3, and generator B2 (voltage v(n4)) produces the multiplier for the v(n1,0) term, region 2. B4 is used as a test, summing the voltages from the B1 through B3 generators. B4 should always produce a unity output after the simulation is started, showing that all regions are covered, and that there are no gaps in coverage, and also that there is no overlap (the sum never exceeds unity).

The graph of the output is shown in Figure 7 following.

Figure 7
Perfect diode region test circuit graph

It is difficult to see the details clearly in Figure 7, however, creating the circuit and running the simulation shows that the results are as desired.

The next step is to modify the circuit of Figure 6 slightly to add the multiplier coefficients, and to place generator B4 (in series with a very small resistor, which is required). Also, the large resistor is deleted. This is performed in the schematic of Figure 8 following. Note again that VF is set to 2v, and VR to 8v, with VIN being a 10V peak sine wave.

Figure 8
Preliminary Perfect Diode Test circuit

The netlist for the circuit in Figure 7 is as follows:

A transient analysis graph of the output is as shown in Figure 9 following:

Figure 9
Preliminary Perfect Diode Test circuit graph

The output may seem a little strange at first glance, but some thought shows that it is indeed correct. During the positive half cycle of applied voltage, when the voltage applied is greater than the selected VF of 2V, current will flow. The peak current will be 8mA. The voltage across this perfect diode model will then be 2V.

During the negative half cycle of the applied voltage, when the voltage is less than -8V, the selected value of VB being 8V, current will flow in the opposite sense to that of the forward bias condition. In this case, it will be 2mA peak.

During the interval when the applied voltage level is NOT greater than VF, and simultaneously NOT less than -VB, the perfect diode model will have a voltage equal to and opposing the input voltage, creating an essentially open circuit to that voltage.

The graph SEEMS to show a linear change of voltage across the diode model during this interval, however, by comparing the input voltage to the voltage across the diode model one can see that they are indeed equal, hence no current is flowing. Actually, there is some slight error due to the program using a Gmin value of conductance across each element, as well as computational rounding of values and numerical precision of the analysis, however, for almost all practical purposes with realistic external impedances it is indeed ideal. It certainly is better than any contrived ideal or perfect modeling using standard SPICE diodes.

Before we continue, it is useful to experiment with this model to cover several other cases. If one wished to create a bilateral breakdown diode, say of 5V, one could set VF and VB to 5V or some other desired value to create such a device. One could create a breakdown diode at a level of +5V by setting VF to this level (and setting VR to some large value. Alternately one could set the breakdown voltage VB to 5V, while setting VF to some arbitrarily large value.

Another interesting element one could make is a programmable reference or breakdown diode. Eventually we will create a parameterized subcircuit model for this device, and VR and VF will be passed values. These values could be variable in value, such that the conduction characteristics could dynamically controlled.

Note that VR and VF could be zero values.

The last step in testing the model is to merge the three condition generators into a single generator. This is shown in Figure 10 following:

Figure 10
Final perfect diode test mode

The netlist for this final test circuit is as follows:

The graph for this test circuit is shown in Figure 11 following:

Figure 11
Perfect diode final test circuit graph

The graph results are as expected, with no surprises. Examination of the graph will show that the N2 voltage tracks the input voltage in the non-conduction region, despite the seemingly linear nature of the N2 voltage. The circuit is now ready to be converted into a parameterized subcircuit, using passed values of VF and VR. A schematic of such a circuit is shown in Figure 12 following:

Figure 12
Perfect Diode final model schematic

The netlist for the model for Figure 12 is shown in the following:

Using this netlist one can create a parameterized subcircuit for this model. It is expected that the folks at B2SPICE will see fit to add this part to their library, for consistency of use of this device if needed.

Conclusion:

An ideal diode model has been easily created using logical equations. This model is perfectly usable, however, caution must be used if two such devices are conducted in anti-parallel. It is usable however as a single level diode clamp circuit, or as a single rectifier diode.

A perfect diode model has also been created using logical equations. This also is usable singly, however as in the ideal diode model, care must be used if two such devices are to be connected in anti-parallel.

Using the techniques shown herein one can create defining equations for such a bilateral clamp circuit and create a suitable model by defining the performance over its regions of operation and creating a logical expression which

The perfect diode model could be used with the proper values of VR and VF to create a bilateral clamp circuit, or a breakdown diode, or a bilateral breakdown diode.
If one needs a bilateral clamp circuit, it is better to use a perfect diode model where one polarity clamp level might be VF and the opposite polarity clamp level VR. These can be passed values.

Why do we need such devices? Do we need such devices? Often in modeling a circuit we wish to simplify the analysis by neglecting parasitics, or, we wish to create a behavioral model for a device, sub-system or system. A behavioral model is a simpler circuit which performs in the manner of the real circuit without all the complexity. These devices can be used in this manner.

Logical equations CAN be implemented in B2SPICE (and other SPICE3 compatible products) to model many such interesting devices and circuits. The techniques to do this have never, to my knowledge, been described and published anywhere, before my articles.