Logical Expressions - erroramp2
About the writer: Harvey Morehouse is a contractor/consultant with many years of experience using circuit analysis programs. His primary activities are in Reliability, Safety, Testability and Circuit Analysis. He may be reached at harvey.annie@verizon.net. Simple questions for which I know the answer are free. Complex questions, especially where I am ignorant of the answers, are costly!!!
Summary: In previous articles of this series I showed how to create logical expressions. In this blurb I show how to prepare an error amplifier model useful with SMPS controller chips. There will be another error amplifier model (erramp) prepared for that set of articles, however in some ways this model is more suitable.
Erramp2:
Why would one wish to create such a circuit? Often when one uses a behavioral model for a device (particularly IC realizations), the linear range of the device is unlimited. But in the 'real' circuit the voltage excursions cannot exceed the power supply 'rails'. Now one could use a 'real' opamp model, but it will add to the complexity of the overall circuit and will simulate slowly. And the 'real' opamp chosen may also not represent the actual device implementation within a controller chip, and it might not work well with the internal voltages within the controller chip as well. Indeed, most of the parameters of the internal amplifier might be poorly specified on the controller chip data sheet.
Yet, for current mode SMPS controller chip modeling, the error amplifier gain is a crucial parameter. And often the voltage excursions of the error amplifier are important as well. Alternately, even when the error amplifier (or compensation amplifier) is external to the controller one may wish to use a simplified model to ease simulations. Consequently, erramp2 was created to produce an error amplifier with a controllable gain, as well as voltage excursion limits. I might have also chosen to include an R-C voltage divider at the output to limit the gain bandwidth, but this would have added some complexity. As the model was chosen primarily to be used within SMPS controller chip realizations, which themselves be turned into a sub-circuit, it did not seem necessary to include this as they could easily be added externally to the error amplifier.
Erramp2 model:
There are several ways the device could have been modeled. I could have used a controlled gain error amplifier. The excursions could have been limited by clamping the output with a bilateral clamp circuit, or a feedback element could have been devised which would limit the output voltage levels. It seemed easier to implement it directly with logical expressions.
What I chose to do is to determine the possible output states and devise equations to represent those states. The expressions themselves could have been written in several ways, however, as no real simplification seemed evident, and the model did work as intended, alternate implementations were not explored.
Consider a simple opamp model with a non-inverting input Va, an inverting input Vb, and an output Vo. Excluding such effects as slew rate limiting, five states are evident. They are:
1. Va = Vb
2. Va > Vb, but we are within the linear region
3. Va > Vb, but the product of gain and (Va - Vb) is greater than Vopl
4. Vb > Va, but we are within the linear region
5. Vb > Va, but the product of gain and (Va - Vb) is less than Voml
Vopl is the maximum positive output voltage limit, and Voml is the negative output limit.
Inspection of the states reveals that states 2 and 4 are are the same, governed by the same result, namely Vo = G(Va - Vb). Moreover, state 1 is a subset of this state.
The equations we wish to create, three in all, are as follows:
IF (Va>Vb) and G(Va - Vb) > Vopl THEN Vo = Vopl
ELSE
IF (Vb>Va) and G(Vb - Va) > -Voml THEN Vo = Voml
ELSE
Vo = G(Va - Vb)
The equations thusly combined, become:
Vo = IF (Va>Vb) and G(Va - Vb) > Vopl THEN Vo = Vopl - G(Va -Vb)
+ IF (Vb>Va) and G(Vb - Va) > -Voml THEN Vo = Voml - G(Va - Vb)
+ G(Va - Vb)
To be honest, it took a little bit of time and effort to create these expressions in their final form, as shown in the results in Figure 1 following:
Figure 1
Erramp1 circuit model
In this circuit the values which will eventually become passed parameters are shown in the equation for B3 generator as constants. A suggested symbol for this device is also shown.
A test circuit for this model is shown in Figure 2 following:
Figure 2
Erramp2 test circuit
There are actually two instances of erramp2 in this test circuit. What happened is that I debugged the erramp2 circuit, and them created a parameterized subcircuit model of the device which I then placed into the circuit. As there are some editing changes required to create the parameterized subcircuit model, it seemed appropriate to include this here, to compare the output results and insure that no mistakes were made in creating the parameterized subcircuit model. The parameterized subcircuit is shown as a subcircuit in the netlist while the model is shown under the main heading.
A netlist for this circuit (remembering that there are two instances) is:
limited finite gain error-amp.ckt
************************
* B2 Spice
************************
* B2 Spice default format (same as Berkeley Spice 3F format)***** subcircuit definitions*limited finite gain error-amp.ckt
************************
* b2 spice
************************
* b2 spice default format (same as berkeley spice 3f format)
* created by harvey morehouse
*
* this model was created for use in smps current mode controller chips where the error amplifier
* gain is an important parameter.
*
***** main circuit
.subckt erramp2 va vb n1
* | | |
* | | output
* | inverting input terminal
* non-inverting input terminal
*
* set the bandwidth using an external r-c voltage divider(s) at the output
*
* if the voltage difference between va and vb is comparatively large the ckt may produce
* unexpected results. do not use this model as a comparator.
*
b3 n1 0 v = u(v(va) -v(vb))*(u( 3.100000e+004 *(v(va) - v(vb)) - 5.000000e+000 ))*( 5.000000e+000 - 3.100000e+004 *(v(va) - v(vb))) + u(v(vb) -v(va))*(u( 3.100000e+004 *(v(vb) - v(va)) + -5.000000e+000 ))*( -5.000000e+000 - 3.100000e+004 *(v(va) - v(vb))) + 3.100000e+004*(v(va) - v(vb))
r1 va vb 1e9
r4 n1 0 1meg
.ends erramp2***** main circuit
B3 N1 0 v = u(v(va) -v(vb))*(u(31000*(v(Va) - v(Vb)) -5))*(5 -31000*(v(Va) - v(Vb))) + u(v(vb) -v(va))*(u(31000*(v(Vb) - v(Va)) -3))*(-3 -31000*(v(Va) - v(Vb))) +31000*(v(va) - v(Vb))
R1 Va Vb 1e9
R4 N1 0 1K
V1 Va Vb DC 0 SIN( 0 .001 100k 0 0)
XX1 Va Vb N2 erramp2
R3 Vb 0 1e9
.OPTIONS gmin = 1E-12 reltol = 1E-4 itl1 = 500 itl4 = 500
+ rshunt = 1G
.TRAN 10u 20u 0 .0001u
.END
Note that in the parameterized subcircuit, the default values for G, Vopl and Voml are passed to the netlist.
Figure 3
The result of the simulation
They behave as expected, in that the linear region is centered about the zero crossings of the input sine wave. An astute observer will see that the N1 and N2 outputs have different amplitudes. This resulted from different values of Voml used in the test circuit than those set as default parameters in the parameterized subcircuit model.
It is interesting to see what the effects are of using larger and larger values of input voltage. Eventually unexpected results will occur, due I suspect from numerical solution errors. However, the circuit is intended for use imbedded within a feedback loop, and not as a comparator. Consequently when the Va - Vb difference is small the results are as expected.
Conclusions:
An error amplifier model suitable for use within SMPS controller chip models has been created. It features a controlled gain, as well as settable output voltage excursion limits. By addition of external R-C and other devices, external to the model, or by their addition within another parameterized circuit model if desired, its utility
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