Shockley Diode & DIAC

About the writer: Harvey Morehouse is a contractor/consultant with many years of experience using circuit analysis programs. His primary activities are in Reliability, Safety, Testability and Circuit Analysis. He may be reached at Simple questions for which I know the answer are free. Complex questions, especially where I am ignorant of the answers, are costly!!!

Summary: A Shockley diode (not be confused with a Schottkey diode) is a two terminal, four layer pnpn diode. While not particularly useful in itself, the model technique may be useful in creating a behavioral model for a DIAC, neon tubes and other breakover devices. A DIAC is itself a bilateral device useful for triggering TRIACs. In this paper a SPICE model for a Shockley diode and a DIAC will be created.

Shockley Diode:

A Shockley diode was, in effect, one of the first integrated circuits, albeit it a primitive one. It is just a four layer diode, a pnpn device, as shown in Figure 1 following. However, within this seemingly simple device are hidden two transistors, which behave in a very interesting manner. Please Refer to Reference 1.

Figure 1
Shockley Diode construction

Figure 1 does little to shed any light into the operation of the device.

Redrawing figure 1 using equivalent transistor elements one arrives at a circuit as shown in Figure 2 following:

Figure 2
Redrawn Shockley diode representations

Refer to reference 1. Clearly when the anode to cathode voltage reaches the value of the Vbe of the pnp device added to the npn Vce breakdown voltage, the pnp device has base current and turns on. This causes pnp collector current to flow and npn base current, increasing the npn collector current, which increases the pnp base current. This regeneration causes both transistors to turn hard-on and the voltage to drop precipitously (the external circuit permitting, of course).

Clearly the 4-layer diode is a precursor of the SCR. The Shockley diode represents an open circuited SCR. Now a DIAC is equivalent to two anti-parallel connected Shockley diodes, as shown in Figure 3 following.

Figure 3
DIAC construction

In Figure 3, a 'n' Region is shown in blue, and a 'p' Region in red. If one were to 'split' the physical model vertically down the middle, one would see a npnp device connected in parallel with a pnpn device. Now of course it is really not this simple, but one can get a grasp of what is happening by this artifice.

Reference 2 shows a typical DIAC datasheet.

A typical DIAC characteristic curves is shown in Figure 4 following:

Figure 4
DIAC characteristic curve

In Figure 4, the pnpn characteristic behavior of Figure 2 (or Figure 3) is shown in the first quadrant, while the anti-parallel npnp device (or npnp) behavior is shown in the third quadrant. Together they form a bilateral Shockley diode or DIAC.

One of the few articles showing some model design information is Reference 3, showing an equivalent circuit which 10 components. Other sources can be found on the WEB that provide listings for circuit models of DIACS. However, what is most interesting is the model behavior from Reference 3, shown here as Figure 5.

If this represents the behavior of the Reference 3 equivalent circuit, then it is very nearly equivalent to three piecewise linear elements in the first quadrant (and in the third quadrant) as shown by the sketch of several (idealized) diacs with different breakover voltages, as shown in Figure 5 following:

Figure 5
DIAC Characteristic curves

To make this clearer, assume that the Shockley device was operating starting at the origin, it is a 32 volt breakover device and it is in series with a suitable resistor, and the combination is stimulated by a sine wave. (We are concerned here only with first quadrant operation at this time.)

During the positive half cycle of applied voltage the device will operate over the curve segment OA, being essentially an very high resistance. If however the amplitude of the applied voltage exceeds Vb (32 volts assumed in this case at point B) then operation will shift to the curve Region AB.

In Region AB the device presents a negative resistance. The slope of this negative resistance Region will be selectable in the model, as will be the Vt level. Now operation will continue in this Region until such time as the point B is reached. At this time operation will switch to curve Region BC. Point C represents the maximum current allowed in the Shockley device by the external circuit.

If, when operating in Region BC the device voltage becomes less than B volts, the question becomes, does the operating point move along region AB or BD? In a 'real' circuit, the negative resistance region is unstable. Thus the previous choice would be answered 'BD'.

Consider the graph in Figure 4. IF we were to apply a current source to this device, with the current initially zero and then increasing positively, we would find that there is only one voltage possible across the device for any given current value. Whereas, if we were to apply a fixed voltage to the device, for some voltage levels there could be only one current value, but for others, three possible current values could occur.

Schockley Diode Model:

The first step is to prove the concept for the device. The easiest implementation seems to be using a pwl device, of a piece wise linear source. A model for this device embedded within a test circuit is shown in Figure 6 following:

Figure 6
Shockley diode concept model

Here we have programmed the A1 (pwl) device with a negative resistance model in the first quadrant. Applied is a triangular current ramp from zero to 30 mA. A graph of the output is shown in Figure 7.

Figure 7
Shockley diode concept model graph

In Figure 7 we see the applied current in the top blue trace, and the resultant model voltage in black beneath it. The voltage rises rapidly to the peak voltage. After this point, a negative (incremental) resistance region is reached. After about 3 mS, the valley voltage point is reached, and then a positive resistance region is entered. The voltage increases until the input current reaches a maximum, and then, as the current decreases the device response in reverse is traversed, eventually reaching zero volts as the input voltage reaches zero. The concept appears to be workable.

A model for a Shockley diode based on a pwl implementation is shown in the following Figure 8:

Figure 8
Shockley diode pwl implementation

As was noted, the curve is single valued as a function of current. Now one could use logical expressions to form the three (or more) straight line segments which represent the circuit.

In so doing, device Vam1 measures the device current. Device H1 converts this value to a voltage driving the pwl source. In the pwl device parameters, the x-array values are the straight-line current breakpoints, with the corresponding y-array outputs being the device voltages corresponding to those currents.

A question is why devices R1, R2 and C2 are in the model. The reason for their addition is to aid in circuit convergence. Without these elements convergence is problematic. The pwl output is divided by approximately 2, hence the reported device voltage to element E1 is multiplied by 2 by E1 internally. Now the Shockley diode normally has a unipolar voltage applied. Consequently, the reverse characteristics in the third quadrant are essentially an open circuit, represented in the pwl array values as a segment starting at -150 volts and zero current. The pwl values are:

x-array : [-1e-6 0 2.5e-5 .01 .04]
y-array: [ -1000 0 32 22 32]

The straight line segment from -1e-6 and 0 (amps) in the x-array produces essentially no current. The current value between 0 and 2.5 ua produces a voltage output proportionally between 0 and 32 volts. The current value between 25ua and 10ma will produce a proportional voltage output between 32 and 22 volts. When the current is from 10ma to 20ma (and beyond) a proportional voltage between 22 and 32 volts will be output. In terms of passed parameters, the arrays are:

x-array : [-1e-6 0 {Ip} {Iv} {Ih}]
y-array: [-1000 0 {Vp} {Vv} {Vh} ]

Now in a specific case one might wish to use more curve data points, but for this article and the device we are making, Shockley1, we will use just those items.

The model with a test stimulus becomes as shown in Figure 9 following.

Figure 9
Shockley model test circuit #2

Figure 9 shows the original circuit, some test circuitry consisting of a sine wave 120V source V2. The circuitry could represent a trigger circuit for an SCR (with the gate input represented as R4). The input is a 120v 60Hz sine wave. Figure 10 following is a graph of the circuit response:

Figure 10
Shockley test circuit graph1

In Figure 10 the top trace is the current through the Shockley device Below that is the input voltage at v1 voltage probe in green. Next is voltage at probe v3, the voltage across the resistor R4 (simulating an SCR gate) in blue. Last, in red, is the voltage across just the Shockley device and simulated SCR gate.

During the first input positive half cycle three trigger events occur. This occurs as the starting charge on capacitor C1 is zero volts as is the input voltage. However in successive starts of input positive half cycles the voltage across C1 will be negative.

What is happening is interesting. C1 charges positively. When Vp is reached, the voltage across the Shockley device drops to avout Vv or more. The capacitor is discharged through the Shockley device and resistor R4. However, R3 is large, and cannot sustain current greater than the peak voltage Vp requirements, so the Shockley device turns off and capacitor C1 recharges toward Vp. Now there are limits on C1 and R3 values. If C1(R3) is too large, the voltage at C1 might never exceed the Vp level. Whereas, if R3 is too low, it might provide enough current to prevent the Shockley device from switching off as C1 would never be discharged below Vp. Multiple trigger events can and do also occur if C1(R3) were too small.

DIAC Model:

Using the basic model of Figure 8, two 'Shockley diode' models are connected in anti-parallel, as shown in Figure 11 following:

Figure 11
DIAC Test model

The test circuit is similar to that of Figure 9. R4 represents in this case a TRIAC gate resistance. Normally a TRIAC is driven with bi-directional pulses, which in this case a DIAC can provide. Figure 12 following is a graph of the circuit performance.

Figure 12
DIAC Test model graph

In Figure 12 we see that, with the component values chosen for R3 and C4 that there are three initial DIAC switching events for the first positive half cycle and two thereafter. The topmost blue curve is this case the current through the 'negative' Shockley diode equivalent portion of the DIAC and the lowest red curve the current through the 'positive' Shockley diode equivalent portion of the DIAC.

The second green curve is the input AC waveform. The middle black waveform is the simulated gate drive waveform to the TRIAC represented by resistor R4. The middle maroon curve is the voltage across the DIAC equivalent device (including the resistor R4). There are no unexpected surprises in the results.

Shockley Device Model:

In Figure 8 we have the basic Shockley diode device. This was used to create a Shockley device as shown in the test circuit of Figure 13 following:

Figure 13
Shockley parameterized device test

In Figure 13 we have created a parameterized Shottley devices U1. The AC source V4 is 110V. The parameters passed to the devices U1 and pwl source will have the values shown in Figure 8.

A graph of the circuit is shown in Figure 14 following:

Figure 14
Shockley parameterized device test graph

In Figure 14 the input voltage is the sine wave in black. The voltage across the Shockley device U1, is the bottom green trace. The voltage at the Shockley device model in red. In blue are the simulated Shockley trigger output, while the maroon trace is the Shockley trigger model trigger output.

Close examination shows that the device model outputs coincide.

The netlist for the Shockley device model is:

* B2 Spice Subcircuit
* created by Harvey Morehouse
* this model may be freely used and copied however
* it is requested that the original documentation information
* be retained.
* Pin # Pin Name
* N1 N1
* N2 N2
.Subckt Shottkey1 N1 N2
***** main circuit
R2 N3 0 10
VAm1 N1 5 0
E1 5 N2 N3 0 2
H1 11 0 VAm1 1
A1 %vd(11 0) %vd(6 0) pwl
C2 N3 0 5p
R1 6 N3 10
.model pwl pwl x_array = [-1e-6 0 2.5e-5 .01 .04] y_array = [-10000 0 32 22 32] input_domain = {.01}

Now the question remains, where are the parameterized inputs in the above model?

Remember, as discussed in a previous article, that other SPICE implementations operate differently with netlists than does B2SPICETM. They will take the netlist and operate on it, substituting parameter values before passing it on to the SPICE engine. In this case the parameters provided are passed to the netlist immediately, obscuring some details. The netlist shows:

x-array : [-1e-6 0 2.5e-5 .01 .04]
y-array: [ -1000 0 32 22 32]

Whereas, in the circuit used to create the parameterized part, the corresponding portion of the pwl device shows:

x-array : [-1e-6 0 {Ip} {Iv} {Ih}]
y-array: [-1000 0 {Vp} {Vv} {Vh}]

The device IS parameterized, as can be seen by examining it IF and when it is added to the database by the folks at Beige Bag Software. Double clicking on the device (in B2SPICETM) reveals a list of parameters that can be altered as desired.

DIAC Device Model:

As a first step in creating a DIAC model, the simplest choice would be to use the existing Shockley device models, connecting two of them in anti-parallel. This is shown in the circuit of Figure 15 following as a test of this concept.

Figure 15
DIAC device concept model

Here the values of the devices corresponding to those in Figure 13 are unchanged. A graph of this circuit is shown in Figure 16 following:

Figure 16
DIAC device concept model graph

In Figure 16 we see that simulated DIAC trigger pulses (Vdt in the middle black trace) occur during positive and negative half cycles of the input waveform. In this case, because capacitor C3 does not start at as negative a level as in the Shockley circuit, C3 is able to recharge and re-trigger a second time due to component values used.

So the concept does work, but there is a problem. Namely, that real DIAC devices are not symmetrical. Using this technique allows one to specify tolerances for Vp, Ip and other parameters, but they will be applied to both of the devices U1 and U2 at the same time. What we would like to to independently vary all of these variables. Now as long as one were using discrete unique devices for U1 and U2 this is fine, however for a single device model this is not suitable.

Denoting the forward peak voltage as Vp and the reverse peak voltage as Vpr, it would be nice to randomly allow them both to be high, or low, one high and the other low, and combinations in-between. Now Vp, Ip,Vv, Iv, Vh and Ih are doubtless interrelated to some extent, as would be Vpr, Ipr,Vvr, Ivr, Vhr and Ihr, but independent variation would allow a worst case simulation to occur.

The next step then is to 'extend' the range of the pwl device to allow it to operate in the first and third quadrants, or, for positive and negative voltages with individually selected breakpoints as in the Shockley device model. This is shown in Figure 17 following:

Figure 17
DIAC concept model #2

Here the A1 device arrays are as shown in the Figure. A graph of the circuit in Figure 17 is shown in Figure 18 following:

Figure 18
DIAC concept model #2 graph

In Figure 18 we can see that bilateral triggering occurs. The results are as expected, so the next test is to compare this circuit with one using two anti-parallel Shockley diode models. Now they are not entirely exact copies, in that each of the Shockley diode devices has a very small 'leakage' current in the reverse direction. Moreover, there are more elements in the anti-parallel Shottkey diode model, consequently there is more opportunity for computational errors to occur. Still, they should be very close. The test model is shown in Figure 19 following:

Figure 19
DIAC Model Comparison

In Figure 19 we have selected to plot Vin, the DIAC model voltage Vdm, the Shockley diode model Vsm, the Diac model trigger output Vdmt and the Shockley model trigger output Vsmt. Not shown is a custom plot of the difference between the Vdm and Vsm.

A graph of the circuit is shown in Figure 20 following:

Figure 20
DIAC Model Comparison graph

The two outputs are very close, as indicated by the small difference voltage. Now at first glance about 8 volts difference might seem to be more than a slight difference, however upon some thought, this represents a difference in time between the triggering events. From a circuit viewpoint, any triggering time difference could produce a fairly large magnitude difference, however we are more interested in the difference between the triggering events. Expand the graph, we get that shown in Figure 21 following:

Figure 21
DIAC Model Comparison graph expanded

Figure 21 shows two representative error voltage plots as well as the representative difference voltage plot. The errors tend to vary somewhat, and what is shown is not necessarily totally representative of the worst errors, however the errors do seem to be in part due to numerical solution 'noise'. Close examination of the time difference between the different but corresponding trigger events reveals that they are separated by about 16uS in time, in the case of the second triggering event. Now of course the time of the second triggering event is of course dependent on the time of the first triggering event and the waveform differences between those events.

However, let us use 16uS as a value which would be typical of the error. In that case, the trigger difference per half cycle of a 60 Hz signal would be about 16uS out of 8.333mS, or, about 2 x 10exp(-3) or percentage wise about 0.00002%. Clearly this is negligible.

Consequently it is concluded that either model might be used, but as the pwl DIAC model has fewer parts it will become the basis of the final model.

The model to be turned into a Diac1 parameterized subcircuit device is shown in Figure 22 following:

Figure 22
Final DIAC subcircuit model

A netlist for the model of Figure 22, to be turned into a part, is as follows:

* B2 Spice Subcircuit
* created by Harvey Morehouse
* this model may be freely used and copied however
* it is requested that the original documentation information
* be retained.
* Pin # Pin Name
* N1 N1
* N2 N2
.Subckt Diac1 N1 N2
***** main circuit
VAm1 N1 5 0
E1 5 N2 N3 0 2
H1 11 0 VAm1 1
A1 %vd(11 0) %vd(6 0) pwl
C2 N3 0 5p
R1 6 N3 10
R2 N3 0 10
.model pwl pwl x_array = [{-Ihr} {-Ivr} {-Ipr} 0 {Ip} {Iv} {Ih}] y_array = [{-Vhr} {-Vvr} {-Vpr} 0 {Vp} {Vv} {Vh}] input_domain = {.05} fraction = true

Now, as a last step, the device we created needs to che check against the circuit model used as a source. The test circuit in Figure 23 follows:

Figure 23
Final DIAC test circuit

In Figure 23 the parameterized subcircuit part that was created is shown as U1, designated as Diac1 part name. The response of this circuit is shown in Figure 24 following:

Figure 24
Final DIAC test circuit graph

In Figure 24 we have the nearly identical results as those of Figure 20, however the difference voltage is much smaller in amplitude. In this case the difference seems to be due to numerical solution 'noise' more than anything else. In some instances there is a spike, indicating a switching event time difference, and in others a level difference. However the agreement is better than that found previously.

The resulting device may have tolerances associated with the pwl break point parameter values in both the forward and reverse conditions.


Useful Shockley diode and DIAC device models and parameterized subcircuit parts have been created. These models, with some slight modification, could also be used to represent a neon tube, a tunnel diode and possibly some other abrupt transition devices.


  1. Central Semiconductor Corp. CT-32 DIAC datasheet -

  2. Spectrum-Soft Newsletter Spring 2002, Modeling the DIAC -