SMPS (Part 2) - Buck voltage mode averaged controller modeling
About the writer: Harvey Morehouse is a contractor/consultant with many years of experience using circuit analysis programs. His primary activities are in Reliability, Safety, Testability and Circuit Analysis. He may be reached at email@example.com. Simple questions for which I know the answer are free. Complex questions, especially where I am ignorant of the answers, are costly!!!
Summary: In previous articles building blocks for PWM modeling have been provided. These include the perfect transformer, the variable transformer, logical functions, and magnetic elements. In this part a model for an averaged mode buck SMPS supply will be created using some or all of the ideas of previous articles and especially of the referenced materials.
All models are approximations of real circuits. Their behavior may not be representative of all combinations of controller chips, switching elements and feedback circuits. It is IMPERATIVE, nay, a NECESSITY for all SMPS model behavior to be validated by comparison with the observed performance of the real circuits being modeled.
There are many different models of PWM controllers. Some, which provide PWM pulses, are suited for transient, actual switched PS modeling. These could be largely real device models, or they could be idealized representations of the manufacturer's block diagrams of the PWM controller chip. These models can be used with real switching devices, or with idealized models of the switching devices themselves.
Some specific controller chip models may be found on the net, specifically from ON Semiconductor but also from other vendors. Some of these models have prohibitions against distribution and will not be discussed here for that reason; however an individual is free to use them.
Here and in subsequent parts we will consider only those models that do not have these restrictions. Thus, aside from the general models, the only other models that will be considered will largely be those without those restrictions, and models created from the equivalent block diagrams of specific chips.
Buck SG 1524 averaged model:
Reference 1 provides a block diagram of an SG1524/LTC 1524 Controller chip, shown here in Figure 1 following:
LTC version of 1524 Regulator Block Diagram
(NOTE: TI and other vendors make similar devices with other features.) For this case, we shall be creating an average model of the device, and simplifying the model to remove some complexities present. Specifically, as we wish only to get a value for the duty cycle output from the device (an average or state-space model), the 'T' flip-flop, NOR gates and output transistors are not required. Also, oscillator frequency control, set by external Rt and Ct values, should be known in any given implementation and the value of the oscillator frequency will be passed to the model.
The shutdown feature and the under-voltage shutdown (available in some versions of the chip) as well as the current limit feature will not be modeled. These can be easily added, and may be useful for the transient, switching device model. But at least for now, they will not be modeled.
From Reference 2, a simple current mode controller block diagram is as shown in Figure 2 following:
Simplified Current Mode controller Block Diagram
Now we are getting close to the required functions to be modeled, however, there are some additions and deletions to be considered. First, the chips include a reference voltage within the chip; however it is brought out externally so that the error amplifier reference voltage may be varied externally. Second, other chips include an under-voltage lockout to prevent controller operation until the voltage to the controller reaches a certain level. Third, some chips include a 'soft-start' function that slowly increases the output driver duty cycle at turn-on. Other functions could be included in the model are duty-cycle skipping under severe overloads, overload shutoff, controller chip supply loading and more. The choice of whether or not to include them is up to the analyst.
If the function is used and is of importance to the proper functioning of the overall circuit it should be included, however, it is possible in some cases to include this external to the model. If these functions are present in an exact model, which would probably be the best tool to use to investigate these effects. If however no exact model can be found, they may be best included in this model. It is assumed that these additional considerations are not of importance here, other than the inclusion of a fixed reference voltage source.
Note that in the model of Figure 2 it is shown as a current mode controller. The current mode control can be disabled and the model used in a voltage mode by grounding the ISEN (current sense) input. But IF current sensing IS used, the duty cycle must be limited to less than 50% for stability reasons. This means that the output voltage of the converter (unless a transformer is used) is normally limited to less than half of the input voltage in a Buck application. For this paper current mode control will NOT be included, but to do so is not very burdensome.
We are now almost ready to construct a controller model, but some additional considerations are necessary. First, if we construct an error amplifier with a 'real' device model, it can be overly complex and cause simulation times to be long. If however we use an 'ideal' opamp representation, the device will not be limited in its voltage excursions. The opamp model should represent the device 'rails'. We will use an op amp model from Reference 3 that properly does this.
Secondly, the duty cycle 'D' is usually ranged from zero to unity, representing the fraction of the period of conduction. This value will later be used with a variable transformer model, to control the average voltage presented to the output filter network. This will be automatically computed in the average model variant.
Third, it is assumed that the converter (in the average case) is operating in the Continuous Conduction Mode (CCM), in that the filter inductor current never falls to zero during normal operation. This is because in this instance the value of 'D' presented to the output inductor is an average of the inductor applied voltage effects over a single cycle with two states: namely with the switch conducting and charging the inductor, and the second while the inductor discharges while the switch is open. If there is a third state, where the inductor current falls to zero (during the non-conducting switch interval), the effects of this are not properly represented by the simplest average model.
Fourth, some controllers, the 1524 being one, (Refer to Figure 1) are designed for use in a push-pull application. The internal ramp is thus at a rate twice that of the oscillator frequency, each alternate ramp controlling a separate output. Each single output should not exceed 50%. This will not affect us in our usage of it in a single ended mode with one output transistor used to provide drive. This will be transparent to us, however it is worth noting.
Fifth, some internal storage and delay time should be represented. It is not possible in the real world to have a switch on time that is infinitely variable. Some delay and storage time, both in the controller chip and the switch (or switching transistor it represents) is of necessity present.
Sixth, some of the idealized representations we will be using switch in essentially zero time. This can cause slower simulations or even non-convergence problems. Some smoothing of the outputs should be added with R-C loads where needed to effect delays and to slow transitions. Also, if an idealized switch is used to represent the transistor, its 'ON' resistance should reflect that of the transistor, and its 'OFF' resistance should be sufficiently low (reflecting actual leakage or a resistance sufficient to ease computations while not affecting circuit performance).
we can list the elements needed in our representation.
A properly limited opamp.
2. A comparator function which computes 'D', the switch commanded 'ON' fraction of a period.
3. Delay and storage elements
4. A duty cycle limiting function
5. The variable transformer circuit (for the averaged model)
The elements will be created one-by-one in the following:
first element is the opamp. Reference 3, Basso's
book, provides a configuration that is suitable for our needs in the
averaged model, with some slight modifications for the switching model.
This is shown in Figure 3 (for the average model) in the following:
Clamped average model opamp primitive
The opamp is shown as a parameterized subcircuit, as it may be convenient to save this as a building block for other controller chip models. The formulas are shown to facilitate its use in other models and/or as part of a larger parameterized controller model.
Resistor R1 is not really necessary; still, it is convenient to add it to the primitive as a source point for controlled source G1. Controlled source G1 transforms this differential voltage into a current with a transconductance of 1mA per volt (gain = 0.001. Resistor ROL, whose magnitude is scaled by the current transconductance, establishes the low frequency, DC gain of this amplifier and the desired open-loop DC gain. Capacitor COL, similarly scaled, is used to establish the open loop pole of the device.
The output voltage magnitude across ROL and COL is clamped by the diodes and limit voltage sources shown, to prevent the output voltage excursions from exceeding the amplifier limits.
Transconductance G1 is used to convert the input voltage difference into a small current, to prevent large clamp diode voltage drops causing output voltage excursions from VLOW and VHIGH limits.
E1 buffers this voltage, and provides an output resistance for the
device. Note that with the idealized devices we are creating in out
controller chip model, the output impedance really has no major effect,
however as we might wish to use this idealized opamp with 'real' devices
at some time, and the inclusion is not burdensome to a SPICE analysis
it is included.
The next building block to be considered is the comparator. We will use logical operators to create this device. It will be a simple nonlinear voltage source, with a smoothing R-C filter following it. The comparator uses as inputs a ramp and the error voltage amplifier output to create a PWM pulse. In our case, we wish to arrive at the value of 'D' that represents the 'on' time of the switch, ranging from zero to 49%. The usual way to compute this value is:
D = (Vo - Vlow)/(Vhigh - Vlow)
In line with the model used in the Sandler circuit (Reference 4, Figure 4.3), the controller model is passed the following parameters:
= the sawtooth oscillator period (per half cycle of the sawtooth)
Td = the delay time to the start of the output drive
Ts = storage time of the output transistor(s)
Vp = the sawtooth peak voltage excursion
Vm = the sawtooth minimum voltage excursion
The actual model used in Sandler's book is by Dr. Vincent Bello. As I could not find this exact model in the literature, and it is in an Intusoft library that bears a copyright notice, we will derive our own model for the controller using the parameters passed, which will differ a bit from the Bello model.
The values of Vp and Vm represent the ramp peak and minimum voltage excursions. Vo represents the error voltage. Thus if Vo varies from Vlow to Vhigh, the duty cycle commanded is from zero to 100%. One could compensate for this in our single-ended design in two ways. One obvious way is to change the value of the error amplifier peak output clamp to present the maximum excursion half that to of the ramp peak level used in the comparator function. Another way is to multiply the value of 'D' by 0.5.
As we are using the chip in a single ended application, either solution or any other, such as limiting the error amplifier maximum positive output voltage level to half that specified would also work.
IF we wished to be most general, for a switching model with a push-pull application, we could use the values as specified, with a steering flip-flop and a ramp frequency of twice that of the oscillator. But again, as a tutorial explanation of how to model a single ended Buck SMPS supply, this would obscure the process with details unnecessary for the purpose of this paper. Only if the simplified model did not properly represent the controller chip operation in the imbedded overall model, or were improper parameters passed to the model, due to design or other errors, would this be a concern to us FOR THIS USAGE.
The comparator model is a nonlinear controlled source to compute the 'D' value. The period of the pulse starts when Vo exceeds Rref (delayed by Td). The pulse end is delayed by Ts. This can be computed as:
2D = ((To + Ts) - ((Vo - Vm)/(Vp - Vm))*To + Td))/To
The first numerator term is the pulse end time, while the second numerator term is the pulse start time. The numerator is divided by the ramp period to compute the fractional 'ON' time of the pulse. The average voltage applied to the output is thus this fraction times the input voltage.
This function is so simple, using the values from the controller specification and the error amplifier output that no separate schematic would be presented. There is a problem, however. Namely that Vo could be less than Vm, and yet 'D' would still have a non-zero value. The best way to represent this would be with logical equations, such that, were Vo<Vm, D=0 else D= ((To + .. (Please tell me you DID read the paper I prepared on how to implement logical functions in B2SPICE!!!!!) An easy way to do this would be to multiply the above expression by a term, 'u(u(Vo-Vm)-0.5))' in the non-linear source used to compute 'D', but this is left as an exercise for the reader.
It is assumed inherently that the filter and error amplifier time constants are much longer than the oscillator period. If so, the voltage to the output filter can be represented by a cycle-by-cycle average value. The only major problem is if there is noise present that might perturb Vo during a cycle.
Certainly in a switched mode model it is a valid concern. So much so that the comparator is often 'blanked' at the start of the comparator ramp for several microseconds to prevent switch noise from affecting the commanded duty cycle.
The last item to be modeled is that of the variable transformer. This was described in a separate paper, as shown in the schematic of Figure 4 following:
Variable Transformer Circuit
Some explanation regarding the variable transformer as used in SMPS average modeling might be in order here. Specifically, with a duty-cycle input of 'D' at the control terminals, this device will present to the output a voltage level which is the average of that presented to the output filter over a switching cycle. Given a switched voltage input of Vin, presented for a fraction of a cycle equal to 'D', the output inductor will see a level of Vin for 'D' fraction of a cycle, and (essentially) zero for a time period of '1-D' for the remainder of the cycle. The average voltage is thus:
Vavg = D*Vin + (1-D)*0 = D*Vin
This is precisely what the variable transformer will present at its output terminals, remembering that the basis for this model is an ideal transformer that passes all frequencies including DC equally well.
Vin is applied (in the model shown) at nodes N1 and N2, with the output at nodes N3 and N4, the transformer control 'D' being applied across resistor R1. Note that these designations will change in the overall chip model, with some slight simplifications in several of the sub-elements to eliminate elements not required.
of the elements for our controller chip average model are now present.
These are shown in Figure 5 as follows:
1524 Averaged SMPS model
The model of Figure 5 is now complete. Averaged models are used in an AC analysis, however, the switching, representing a sampled data control system, causes Nyquist errors at intervals of half the switching frequency in the output. Most averaged models including this one do not represent these effects. Models by Ridley, derived in his thesis, or based on his methodology and some others as well do include these effects.
If the error signal at the INV terminal N3 is less than the reference level at the error amplifier input N4, the output will be at a high level. The output terminal of the error amplifier, 'Vea', provides a connection for the external compensation components, between this point and the inverting input 'N3' of the error amplifier.
Amplifier 'B3' and resistor R4 implement the comparator function. Amplifiers 'B1' and B2' with associated components are the variable transformer. The supply level is 'V1' and the output is equal to the product of 'V1' and 'D' at 'Vd'.
A netlist for this simple implementation of an averaged, continuous conduction mode controller circuit is as follows:
DCLAMP D is = 2.55e-9 rs = 0.042 n = .01 tt = 5.76e-6 cjo =
1.85e-11 vj = 0.75
The only interesting thing not previously mentioned is the diode model DCLAMP. Here, the 'n' emission coefficient is set at 0.1. This combined with the very low current output of the 'G1' source will make the diodes behave in a nearly ideal manner.
Because editing of the device library to remove bad models is not possible, before adding this (possibly) erroneous or unsatisfactory model to the library it will be first tested, always a good practice. Thus additional components will be used to connect to what could eventually be subcircuit nodes and test the model.
approximate topology of the test circuit will be essentially to that
of Figure 6 following:
Approximate 1524 Test topology
The variable transformer, shown as 'X2 PWM', is not included as it is present within the controller model. For generality this is NOT a good idea, as the output could be configured in different ways for different topology switching supplies, however this is unimportant for this illustration.
Devices C41, L1 and source V2 are present to enable AC signal injection into the circuit while preserving the DC bias levels.
There is one problem in using our controller model with this schematic, however. Namely, that there is no explicit DC feedback from the error amplifier output to the negative terminal. Without this, our simplified controller may not regulate DC properly. DC feedback does occur implicitly when the overall loop is closed. A resistor could be added across R5 and C2 of Figure 6. A value of 10,000 times that of resistor R4 (22K) or 220Meg could be added which will not affect the DC open-loop gain of the error amplifier. To be slightly more rigorous one could estimate the leakage resistance of capacitor C2. This could be added to the controller model if desired, however here we will just add a resistor to the 'external' components.
Now, using a separate schematic 'page' to connect the added components to those of Figure 5, as shown in Figure 7 following, the first test circuit becomes:
Average mode test circuit #1
A netlist for the circuit is as follows:
DCLAMP D is = 2.55e-9 rs = 0.042 n = .01 tt = 5.76e-6 cjo =
1.85e-11 vj = 0.75
D2_DCLAMP D is = 2.55e-9 rs = 0.042 n = .01 tt = 5.76e-6 cjo
= 1.85e-11 vj = 0.75
.model resistor r res = 1
The above circuit has L2 set to 10Hy and C3 set to a value of 1F, as for this first test we wish to see the DC performance of the circuit as well as the open loop transfer function. Analyzing this in the DC mode we can see that the steady state DC output is 5.000 volts with a 100-ohm load. The output will rise to this value in a few milliseconds.
One can add a pulsed current source across the load to see the effects of a step load on the output, roughly. A better analysis is to add an AC voltage source to V3 to estimate the effects of audio susceptibility.
The preceding example shows in brief how to construct a PWM average controller chip model using just a block diagram and idealized elements. This is described in more detail in the referenced documents. The model created needs more work before it can be really useful.
Unless one has an exact model of a controller chip, one must do something. A good choice is to use one of the 'generic' controller chip models. There are a fair number of them, and some of these will operate in both the continuous and discontinuous conduction mode. Some will show the effects of the Nyquist sampling of the controller in the frequency response characteristics.
The purpose of this paper was NOT to prepare a 'better' model of a controller chip, as the architecture and models will generally fall into a few types better represented by models readily available for use. The problem in using these models is in understanding the required parameters to be passed, their usefulness and their limitations, and converting them into a suitable format for B2SPICE usage. In later papers, time permitting, it is intended that some generic models will be converted and a brief explanation provided.
This will not take the place of downloading information, purchasing and reading materials and studying in the area of SMPS analysis, and one is always learning that there is more and more to learn. But hopefully it will help a willing student to get started. I do not pretend to be an expert in the area of SMPS design nor modeling, but just a willing and eager student.
This set of papers will NOT be a study of state-space modeling nor of Vorperian switch modeling, as better and smarter persons than I have done much already, although I may get brave enough to do this in the future when several of the generic models have been converted and if there seems to be some interest.
1 LTC 1524A Datasheet, http://www.linear.com/pdf/lt1524.pdf
2 Write Your own generic SPICE Power supplies controller models, by Christophe Basso, http://www.eetasia.com/ARTICLES/2002APR/2002APR19_POW_EDA_AN.PDF