Summary: In previous article a simple illustration was provided showing how one could create an idealized controller model from a controller chip block diagram. Here we shall show how to convert an existing, generic switched controller model into a B2SPICE (or any other SPICE3 product) compatible format.

Converting an existing Generic Controller Model:

One good collection of Christophe Basso controller models (and others he converted) is found in Reference 1. We shall be looking at the model he calls PWMCM, in the pSPICE collection. The name implies it is PWM model for a current mode controller. We shall rename it to be SPWMCM, where the leading S denotes a Switched model as compared to an Averaged model. His model is:

Unfortunately, the model(s) refer to other imbedded subcircuit models. Fortunately they are shown or described in other articles, and/or in his book, Reference 2. The subcircuits we need to create for this specific model are XERR (model ERRAMP), a current limited error amplifier, XCOM (model COMP), a comparator, XFFL1 (model FFLOP), an RS flip flop, XOR2 and XOR3(model OR2), an 'OR' gate, SFFL2 (model TOGGLE), a D fflop. As these devices are used in many of his models, it is convenient to create them as separately as subcircuits which can be reused. In this manner we may just call them from a netlist or if we create a schematic, add these devices. We will convert several of these subcircuits, even though they are not required for this specific conversion.

We also need to translate a logical equation, E_BOUT 15 2 VALUE = {IF( V(81)> 3.5, {VOUTHI}, {VOUTLO})}, into a B2SPICE compatible format. The equation reads, IF V(81) > 3.5 then E_BOUT = (passed parameter) VOUTHI ELSE E_BOUT = (passed parameter) VOUTLO. As this will be implemented as a non-linear source, it is convenient to convert this first. But we shall first change the equation slightly to reflect that an 'ELSE' is not directly realizable in B2SPICE.

Our realization will implement the equation, V = {VOUTLO} + u(V(81,0)-3.5) * {VOUTHI - VOUTLO}. The output thus will be equal to VOUTLO unless V(81,0)>3.5, in which case the output will be VOUTLO + (VOUTHI - VOUTLO), or VOUTHI after adding the terms.

Because some of the more complex subcircuits will require use of simpler ones, we will start creating subcircuits of the simpler ones first. The first is a 2-input comparator we will name as COMP to conform to the Basso listings. The original netlist is:

The schematic for COMP is shown in Figure 1 following, together with applicable equations and a symbol for the subcircuit. At this time there is a choice to be made. Sometimes for some chips the equivalent circuit shows a flip-flop, gate or other device driving a switch transistor or other circuitry. The best realization would require that the output drive capabilities such as high output levels, drive current capability and so on be capable of being modified to reflect the actual switching mode controller capabilities. We will NOT do this. Should such a requirement be present, it can be added by using an output buffer device tailored to the need. Also, the whole purpose of simplified generic models is to create somewhat idealized representations of switching mode power supplies to enable fast simulations to be performed.

Figure 1
COMP schematic, equation and symbol

It should be trivial for a reader to add this part to the database. Although it is assumed this will be added at some time to the standard library, it is also assumed that the reader is able to do this and will do it, in order to fully go through this article, as well as to enable this and other Basso or SMPS controller circuit models to be imported into B2SPICE.

The netlist for the next device to be modeled is AND2, whose listing follows.

The schematic, equations and symbol for the AND2 subcircuit are shown in Figure 2 following:

Figure 2
AND2 schematic, equation and symbol

The netlist for the next device to be modeled is NAND2, whose listing follows.

The schematic, equations and symbol for the NAND2 subcircuit are shown in Figure 3 following:

Figure 3
NAND2 schematic, equation and symbol

The netlist for the next device to be modeled is NAND3, whose listing follows.

The schematic, equations and symbol for the NAND3 subcircuit are shown in Figure 4 following:

Figure 4
NAND3 schematic, equation and symbol

The netlist for the next device to be modeled is NOR2, whose listing follows.

The schematic, equations and symbol for the NOR2 subcircuit are shown in Figure 5 following:

Figure 5
NOR2 schematic, equation and symbol

The netlist for the next device to be modeled is OR2, whose listing follows.

The schematic, equations and symbol for the NOR2 subcircuit are shown

Figure 6
OR2 schematic, equation and symbol

The netlist for the next device to be modeled is INV, whose listing follows.

The schematic, equations and symbol for the INV subcircuit are shown in Figure 7 following:

Figure 7
INV schematic, equation and symbol

The netlist for the next device to be modeled is TOGGLE, whose listing follows.

Note that in the implementation there are two different NAND3 models used. There is a version with the output capacitor initial condition set to 5V and another with the initial condition at 0V, logic 'ONE' and logic 'ZERO' respectively. Why is that?

If one were to use a single NAND3 device model, they would be identical, and would initialize and tend to go to an identical DC state under certain conditions, causing convergence difficulties. These devices exhibit NO hysteresis, and the trip point would be identical for the logical equations which form the 'guts' of the equation. Moreover, the DC output level is provided by a solid 5V, not a source which could, by source stepping, alleviate this problem in some cases. The solution Chris Basso used is to set the initial conditions differently. NOTE that IF the state could be truly indeterminate in some cases, that one would have to have two different models for each NAND3 pair of a latch implementation, and multiple combinations would have to be used to cover all of the cases. In the case of three latches, as in the TOGGLE circuit, one MIGHT have to use eight combinations to cover all of the cases.

However, good design will reset logic devices to a known state, at least once the circuit stabilizes and a DC operating point is reached. Consequently the initial conditions being different will merely aid in convergence. Another solution, which has the same effect, is to slightly alter the implementation such that the gate pairs in a latch are not identical in start-up operation by adding a small resistive loading to one gate. IF the analog circuits we used to model logic devices had input impedances, and the 'Q' output were loaded with a different number of gate inputs than the 'QB' output or other loads, this would eliminate this problem. One could also make the models unique in a given implementation, with different initial conditions.

I chose to rely on the addition of resistors, where needed, to insure that the devices are slightly different and enable easy convergence. The effect is the same, but only a single NAND3 model is required at the expense of adding extraneous resistance(s).

Figure 8
TOGGLE circuit schematic

The basic circuit consists to two latches. The first is set during the clock input TRUE interval, and at the negative transition of the clock pulse the contents of the first latch is transferred into the output latch. The test circuit (corrected)for this circuit is shown in Figure 9 following:

Figure 9
TOGGLE test circuit schematic

The netlist for the next device to be modeled is FFLOP, whose listing follows.

The schematic, equations and symbol for FFLOP are as shown in Figure 10 following.

Figure 10
FFLOP circuit, equations and symbol

This model proved interesting to create. One would believe that the model would be quite straightforward, and indeed the latch portion is just two interconnected NAND2 devices. However, the problem comes with the inversion of a logical function, namely, using the inverse of a 'u' function in an equation. Given a function

     f(v) = u(v(t))

The logical INVERSE of this function is NOT -u(v(t)). Clearly the output varies between zero and some constant value, in this case unity. Negating it creates an output that varies between zero and the negated constant value. The function

      f2(v) = u(-v(t))

will not work correctly in most instances if the argument is unipolar logic expression, as the same effect occurs. What we need is a logical inverse of the signal, not the arithmetic inverse of a signal. This is the function of the B3 and B4 generators. These functions could of course be incorporated into the B1 and B2 sources, however for simplicity and as an aid to understanding, separate generators were used. It would be instructive for the reader to attempt to construct their own model for an RS flip flop.

We have created a (logical) inverter model as 'INV' which could have been used with NAND2 devices to create the RS flipflop, however it seemed more reasonable not to use a sub-subcircuits in the implementation as intuitively it seems this would add to the computation time by some amount.

NOTE: All of these logical devices in this article are actual ANALOG device implementations, and one must take care in using them with both analog and digital device implementations. One or the other 'loadings' of the devices are acceptable, as there is an implicit DAC or ADC added to the output, but the output cannot be both at the same time. Also, if DIGITAL devices are used with the logic device models created herein, one will have to adjust the digital device values under the SIMULATION/MIXED MODE menu options. IF an output drives BOTH (true) digital and analog devices, an ideal non-inverting buffer must be provided to isolate the different loadings.

At first it was intended to include the XERR ERROR AMPLIFIER MODEL as a part of this article, however it became too lengthy to do. This will be done in SMPS part 4, where we will examine some implementations using that model. However, as the BB folks have been good enough to include some of these building block models in their library, and as it does require some time to proofread and edit the article, not to mention add the devices to the library, it was concluded that many persons could build on what has already been done to create their own SMPS device models. And, while this is occurring, it seemed worthwhile to digress a bit to discuss some convergence issues in a separate article (and whatever else might seem worthwhile, time permitting).

References:

1. Christophe Basso Web site, http://perso.wanadoo.fr/cbasso/Spice.htm

2. Switch-Mode Power Supply SPICE Cookbook, by Christophe Basso

3. SMPS Simulation with SPICE3, by Stephen M. Sandler