Summary: In a previous article we showed how to convert existing, generic switched controller device models into a B2SPICE (or any other SPICE3 product)compatible format. However, one element was not created, namely the ERRAMP1 model. This will be created here.

Converting an existing erroramp model:

One good collection of Christophe Basso controller device models (and others he converted) is found in Reference 1. We shall be looking at the error amplifier model he calls ERRAMP, in the file named PWMCM, in the pSPICE collection. His model (with the pertinent part in bold italics) is:

This is similar to the clamped opamp in the previous part, but with current sink and peak current information.

One might ask why we need a clamped output opamp. Or even why we need to worry greatly about the gain? The answer is that a current mode controller is sensitive to the gain of the error amplifier. The amplifier shown here has several other features that could be useful as a general basis for modeling a switching mode controller with a transistor switch.

If the error changed abruptly, then the error amplifier might reach internal limits of current and voltage that would change the output response from an ideal, unlimited case. Now in general you are NOT going to find this information in most controller chip data sheets. If you can, it will be useful to include this information. If you are creating a averaged model, you would still wish to select the opamp gain and voltage limits, as we would then wish to create a level corresponding to a duty-cycle input to a voltage variable transformer.

His model, shown as a schematic (but with no netlist) in Christophe Basso's book, reference 2, is as follows:

Figure 1
ERRAMP model

The preceding shows the model with the required parameterized inputs and the following values for the passed parameters:

This model is fine, but I believe it can be made better. We will be making some slight modifications to it.

The B2SPICE model for this device is shown in Figure 2 following:

Figure 2
Modified Erramp model

In Figure 2, the input is applied across the NINV (non-inverting) and INV (inverting) terminals. Rp is set to equal GAIN (in ohms), and Cp is set to equal 1/(2*Pi*GAIN*POLE) - in farads. The GAIN is the open loop gain of the device. POLE is the low frequency break point of the device.

Now in Chris Basso's model he used a factor of 10-4 in the G1 device. This same value divided the value of Rp and multiplied the value of Cp. The purpose of doing this is that the voltage clamp circuit used a 'real' diode tweaked to make it more ideal. By multiplying the elements to make their impedances larger, the imperfections of the clamp diode circuits can be made of lesser importance.

However we have 'perfect' diodes that do not require this artifice. Consequently, we can make the transconductance amplifier G1 gain equal to unity as opposed to his value of 10-4.

The current provided by G1 produces a voltage across Rp and Cp equal (at low frequencies) to Vin*Rp volts, where Vin is transformed into a current. As Rp is equal in value to the open loop gain, the low frequency gain is equal to GAIN (internally before output voltage and current limiting). At the frequency (POLE) value of 30Hz in this case, the gain is 3dB down, diminishing at 20dB/decade.

The perfect diode model allows the forward and the reverse breakdown to be set to exact values, with essentially no resistance in either case. In this case, one can set the breakdown voltage to -VLOW, and the forward voltage to VHIGH to limit the output to between VHIGH and VLOW in excursions.

On Chris's model D14, V4, IS and Q4 are used to set the sink current of the amplifier, while I2 and D12 set the source current limits for the device. However, there is no reason why we cannot use two current sources paralleled by 'ideal' diodes, in series, eliminating those devices.

The current limiting is interesting. If the source B1 is providing no current, then the currents of sources Isl and Is circulate entirely in ideal diodes U3 and U4. When the current from B1 is less than ISOURCE, it flows through forward biased diode U3, and also forward biases diode U4 by that same additional amount. When the load attempts to draw more that ISOURCE, then U3 is turned off and Is provides just ISOURCE to the load through U4. When B1 is sinking current, the opposite occurs, except that the current is limited to ISINK through source Is as a limiting value.

The values of the perfect diode were set to be a reverse breakdown voltage drop of -VLOW volts and a forward drop of VHIGH volts. This represents the case where a unipolar supply is used for the amplifier. (If we were using an opamp with positive and negative supply output rails of +5 and -5 volts, we would set the forward voltage and reverse breakdown voltage drops to approximately 5V and -5V respectively.)

To fully test all of the device features, several tests are required. The first test will examine the output voltage levels, and current values. Refer to Figure 3 following:

Figure 3
Modified Erramp model test1 circuit

In the circuit of Figure 3 we are using a 10Hz, 1V signal input. The load is contrived to produce charge and discharge current values that will cause current and voltage limiting to occur. A graph of the output is shown in the following Figure 4.

Figure 4
Modified Erramp model test1 graph

Although not totally clear, during the negative input interval the capacitive load is provided 0.5ma until the time that the load capacitor reaches 2.8 volts, after which the load is provided just enough current to maintain the output at 2.8v. During the positive going input interval, the load capacitor is discharged at a rate equal to or less than 15ma until the capacitor voltage reaches 0.1V. The output level excursions are between 2.8V and 0.1V, and the circuit behaves as expected.

The second test modifies the output levels to +5 and -5V. The load diode was reversed, and RL was set at 1K . Lastly, the positive and negative current excursions were set at 15ma. To ease convergence the internal resistance of perfect diodes U3 and U4 were set at 1 milliohms. A graph of the circuit with these changes is shown in Figure 5 following:

Figure 5
Modified Erramp model test2 graph

In Figure 5 we see that the current pulses are symmetrical, and of 15ma amplitude. During the positive input interval the load current is just slightly less than 5ma (due to the internal ROUT value of 10 ohms). The output excursions are between +5 and -5 V.

The next test will be with the original default passed parameters, but with a zero offset sine wave error voltage of 1V in amplitude. The amplifier will be connected in an inverting configuration with a forced gain of two. The circuit is shown in Figure 6 following:

Figure 6
Modified Erramp model test3 circuit

A graph of this circuit is shown in Figure 7 following:

Figure 7
Modified Erramp model test3 circuit graph

Initially, this seems correct. When Vin is positive, the output clips, and when it is negative, we get a positive half sine wave output. However, on close examination, we do not get a full half-wave amplified sine wave output. The peak is -2 times that of the input, however. What is going on?

Well, we have to consider that a virtual ground is only present when the forward gain is large. And, when the output is clipping, the gain is essentially zero!! Consequently, during the time when the input voltage is positive, and some of when it negative, the input signal is fed forward through the feedback resistance to the output. Normally we would not expect the error voltage to do this, but this is always a possibility. During this time the virtual ground is not present.

It is interesting to see what happens when the product input voltage level and the forced gain input signal exceeds the maximum allowed voltage excursions. Setting the input level to a 2V sine wave, we get the graph of Figure 8:

Figure 8
Modified Erramp model test4 circuit graph

In Figure 8 the loss of gain is clearly shown during the negative signal excursions. The point is that sometimes-anomalous results can occur in a simulation, and it behooves us to understand why they occur - most often due to construction or misunderstanding of the results under unusual conditions of operation.

The circuit could take some more simulation and testing to validate the results, and this has been done, however, it is left to the interested reader to delve into this in more detail. Operational amplifiers that have unipolar supply levels are often tricky and misunderstood.

Summary:

A model of an error amplifier has been prepared, which is loosely based on the model provided by Chris Basso. Several of the operational features of this model have been examined and discussed. This model should be placed into the standard library as a parameterized subcircuit model for use in SMPS models and in other places where a more exact model is not required.

References: