Summary: In this article a preliminary controller chip model was created, along with some other useful elements, which may be used to create other controller chip models. The model here is NOT complete and an error was noted which is present in the model. Nonetheless it illustrates some of the thinking and steps required in creating a controller chip model.

LT3430 Datasheet Model:

Refer to Figure 1 following, which shows the block diagram for an LT3430 current mode controller chip. This was taken from the LTC datasheet for this device. It is rather interesting in that it has some unique elements shown.

Figure 1
LT3430 datasheet block diagram

The LTC datasheet for this device is reference 1. The device has a frequency control within. For very light loads, where the minimum attainable duty cycle (due to delays and storage times) would cause cycle skipping and undesirable ripple effects, an internal provision is made wherein the frequency will be lowered. There is also a foldback current limit, which serves to limit the output currents when the output is short-circuited. Other interesting features are the shutdown which has a dual mode, the synchronization feature, and a patented anti-slope current compensation scheme which is said will allow larger output currents for certain cases where the slope compensation would otherwise limit the inductor current.

The controller is a current mode controller. For those not familiar with current mode control, the differences are interesting. The output error voltage, applied to the FB input is compared to a fixed reference. When the reference is greater than the FB input, the output transistor is nominally turned off. However, a second feedback loop is present and is shown by the current comparator, which compares the error voltage to the current through the switch transistor. What this does is to turn off the switch when the current limit is exceeded. Moreover, the error signal has another signal, a slope compensation (ramp) signal, which subtracts from the error voltage.

The net effect of this is to apply a variable current to the output inductor. The current ramp, which is subtracted from the error voltage, will modify the output duty cycle. This compensation ramp and its slope is very important to operation for duty cycles greater than 50%, as current mode controllers are unstable under those conditions.

This is better seen from the circuit in Figure 2, which is a generic current mode controller.

Figure 2
Generic current mode controller

Figure 2 is taken from reference 2, which is well worth reading and understanding.

The differences are small between that of the generic current mode controller and that of Figure 1, namely the frequency control functions, the shutdown function and the arbitrary inclusions of the slope compensation and inductor current waveforms without a source for those signals. The block diagram of Figure 1, and its datasheet unfortunately do not include much information necessary to create a chip model. As was noted, and as shown in reference 2, the error amplifier gain as well as the compensation ramp slope is very important to proper circuit operation.

However, the compensation ramp slope maximum for proper operation can be deduced. In Reference 2, 'm2', the discharge slope, is approximately equal to Vo*Rs/L. In this case, we INFER that the 'L' value is chosen from the allowable range on the data sheet as being equal to 5 x 10E-6. Rs is set at .150 ohms, and Vo is chosen as 15v (as the data sheet infers), producing m2 = 15*0.15/5e-6, or, 0.45 x 10e6 volts/sec.

From equation 4, the error amplifier gain 'A' should be greater than T*Rs*Vo/L. This equals 2.25. But, there is a voltage divider gain, which should be factored in. Using a value of 1.22/15, or 15 as a worst case, the gain should exceed 34. We will use a gain of 35 as a minimum, which of course the error amplifier easily exceeds.

From equation 3, the compensation ramp down slope 'm' should be greater than (1/2)*m2, or 2.25v in 50 us.

The following assumptions are made:

1. Only total shutdown will be modeled.
2. Over-current limiting will not be modeled.
3. Temperature effects will not be modeled.
4. A smooth switch with series resistance will represent the switching transistor.
5. For simplicity, a modified version of Figure 1 will be used.
6. 'A' will be scaled for the minimum recommended value of 'L'
7. Single frequency operation will be modeled.
8. The patented anti-slope modifications will not be modeled.

If any or all of these considerations are important, or any others for that matter, it is possible to add/modify them without too much effort, save for 3, 4, 7 and 8, which would appear to present an increasing order of difficulty. (As an example, consider the error amplifier in the block diagram of Figure 1. To model this fairly accurately would require some thought and effort, as well as some characteristics of the devices involved.)

Simplified LT3430 model:

A slightly modified circuit based on Figures 1 and 2 will be created, but first in order to do so five logical elements need to be made for the realization I have chosen to make. While these could (and will) be modeled with more primitive behavioral elements already created (see the SMPS articles in the B2SPICE resources section) they will clutter up the diagram with details and for clarity they will be created as single devices. The five elements are an (analog representation) of a Leading Edge Detector (LEdet), the second is a square wave to ramp converter (LE2R), used to create the compensation ramp signal, and the third a two input summing device (SUM2), an Operational Transconductance Amplifier or OTA (OTA2, based on the OTA1 device and article), and a Trailing Edge Detector (TED).

I chose to use a single generator to create a square wave signal, operating on that signal to produce a wave train of pulses as well as a sawtooth signal. Thus a single generator/parameter could be used to vary the switcher frequency, opening the way for possible modeling of the variable frequency operation characteristics of the device at a later time if needed.

The LEdet device circuitry is shown in Figure 3 following:

Figure 3
Leading Edge Detector Circuit

The circuit is very simple and straightforward. Internal delays in devices U1, U2 and U3 cause the input signal, when triply inverted at node N3 to go false after some delay when the 'IN' signal is asserted. Thus at the leading edge of the signal applied to the 'IN' port of the device will appear at the output of the 'AND' gate. The output signal will be slightly delayed due to an RC delay incorporated into the AND gate model. This model uses a threshold of 0.8 volts (arbitrarily) as a threshold point with no hysteresis. The models were described in previous SMPS articles and will not be otherwise discussed here. A circuit for simulation of this device is shown in Figure 4 following:

Figure 4
LEdet test circuit

In this case we are applying a 200 Kc square wave to the circuit. The devices were set to provide a zero to +5V amplitude output signal. The actual amplitude in this case is not important, as the circuit will not directly drive outputs that are sensitive to this parameter. The logic elements have their own imbedded ground, as well as input and output return paths to ground. Consequently the inputs can be driven from voltage sources or from voltages referenced to ground without worrying about adding termination resistances to ground. Similarly, the outputs need not have a return path to ground.

A subcircuit was created from the netlist and added to the library with the name LEdet, under a behavioral category. The symbol for this device, after adding it to the library, is shown in the test circuit of Figure 4 driven by the same generator as the model. The purpose, of course, is to show that there were no errors made in creating the part from the subcircuit.

A graph of the output is shown in Figure 5 following:

Figure 5
LEdet test circuit graph

It is not entirely clear from Figure 5, but the outputs V(OUT) and V(OUT2) do coincide. It is important to note that the circuit MIGHT be made using models of actual devices, but this is NOT to be done in this instance. Depending on the exactness of the models chosen for the devices, this could add significant time to the simulation. Moreover, if the devices were digital devices, a digital to analog converter would have to be added to the output of the device, if only implicitly, were the output to drive analog devices. If the device were to drive both digital and analog outputs, a buffer would have to be added to one or the other of the similar outputs, as a device cannot drive both analog and digital devices at the same time.

The next needed device is one that will convert the same square wave stimulus used for the LEdet circuit/device into a sawtooth ramp, LE2R. Several methods of doing this seem possible. One would be to convert the square wave of voltage into a square wave of current, and use this to charge a capacitor. Of course this would only create a half of a sawtooth of voltage, and one would have to discharge the capacitor. Now one could invert the input voltage, and create the other half of the wave, with an appropriate discharge circuit, and sum the two signals.

Another way would be to use the LEdet output to control a current generator and a switch. The current generator will charge a capacitor through a series resistance, creating a ramp of voltage. But when the LEdet output is true, a switch will be closed, discharging the cap through a very small resistance, resetting the ramp. This seems to be much simpler to implement, and will be the scheme used.

The circuit for the LE2R is shown in Figure 6 following:

Figure 6
LE2R model

In this model B1 generator has a 1A current amplitude, and switch S1 closes momentarily when the input is true. The smooth switch used is a modified STSNOT1 device (described in another article in the Resources section of the B2Spice webpage, under the Boolean Algebraic Expressions, Number 8. Because the signal has to reset very rapidly, because of the 50 us period, the expression for the STSNOT1 device, ST1, was edited to produce a value for the current generator of:

B1 N1 N2 i = uramp(v(n3,n4)-.1)*v(n1,n2)*10000

The voltage output of the LE2R device should have an amplitude of 2.5V in 50 us. As I = C * delta V/Delta T, or, 1 = C * 2.5/50e-6, C = 20 UF.

Thus, a negative going sawtooth compensation ramp of about -1.25V amplitude with a period of 5u seconds is created.

The amplitude of the output was chosen to exceed the minimum requirements of reference 2, with an output voltage equal to 1.23V, and an inductance value 'L' of 5u henries. Rs was chosen as 0.1 ohms to agree with the values of the data sheet for the nominal current sense resistor, and to provide an amplitude which was within the internal logic level of 2.9 volts. (The voltage limited error amplifier will also be set to be within this voltage range.)

A test circuit for this device is shown in Figure 7 following:

Figure 7
LE2R test circuit

In this case the circuit shows the LE2R part created from the circuit as a test of the creation of the part creation process and to ensure that no errors were made. A simulation of this circuit is shown in Figure 8 following.

Figure 8
LE2R circuit simulation

The outputs are as expected, with v(OUTR) and v(OUTR2) outputs coinciding. The square wave source is shown for reference. Not shown is the LEdet pulse output, which occurs at the positive going transition of the v(6) source.

The next device to be created is the SUM2 function, which is very simple. This is just a nonlinear controlled source, which creates the arithmetic sum of two signals. The circuit for this device is shown in Figure 9 following:

Figure 9
SUM2 circuit

The signals to be arithmetically added are applied at the 'IN1' and 'IN2' terminals, with the arithmetic sum presented at the SUM2 output. The nonlinear dependent generator B1 has as its expression v = v(IN1) + v(IN2).

A test circuit for this device is shown in Figure 10 following.

Figure 10
SUM2 test circuit

Source V1 is a negative going ramp generator, and V2 is a sine wave generator. A graph of the simulation of this circuit is shown in Figure 11 following:

Figure 11
SUM2 test simulation graph

In Figure 11 the input negative going ramp is shown, together with the input sine wave. These are added arithmetically in the circuit, as well as in the part created for this circuit, with the outputs v(SUM2) and v(SUM22) coinciding and overlapping. The results are as anticipated.

The next device to be modeled is an Operational Transconductance Amplifier, or OTA. I had considered using a conventional error amplifier in the model, however then one would have had to sense the nature of the compensational network, or to create an uncompensated error amplifier output voltage, convert it to a current, and apply this current to the external compensational network. It is easier just to use an OTA directly.

In the OTA model we might need to include output voltage limiting as well as maximum output current limiting. OTA1 is a more primitive version of the OTA without output voltage limiting hence the OTA2 model will be used.

It should be noted that with the unipolar version of an OTA the output voltage will be limited to voltages between essentially ground and the positive supply voltage. But, the output current is bi-polar, both positive and negative in sense, while the output voltage is constrained. This means that the circuit should be capable of discharging capacitance at the output to essentially ground, and that the output current slew rate should be the same for both positive and negative going levels.

I used a 'perfect diode' implementation to limit the output voltage excursions. (The perfect diode is described in one of my articles in the B2SPICE resources WEB page.) The forward voltage was set at the output voltage maximum value, while the lower limit was set to zero. While it would have been nice to set the lower limit to a small positive value (for the output sink capability of the OTA) it was felt to be of no practical significance.

Another consideration is that the device is typically limited to voltage differences at the input terminals to magnitudes between about 0.1 to 0.3 volts for linear operation. I attempted to include such limitations in the model but it became burdensome to include. If significant performance differences are noted between my model performance, and those of the LTC model (as used in the LTC version of SPICE) then this may be added at a later date.

The model for OTA2 is shown in Figure 12 following:

Figure 12
OTA2 circuit model

The model is based on the OTA1 model. The transconductance of the B1 generator will be the product of a passed transconductance gain 'G' and the voltage difference (v(INp) - v(INm)).

ROUT and COUT represent parasitic effects in the OTA, which determine the device open loop characteristics. Figure 13 following is a test circuit for the OTA2 device. The diode PD1 is a perfect diode. Its forward voltage drop is 'vd' representing the maximum output voltage, while the reverse breakdown voltage is set to a small value. This will actually be a small negative value.

Figure 13
OTA2 test circuit

The test circuit consists of the circuitry used to create the OTA1 and OTA2 models as well as the OTA2 device that was created, so that we can compare the three outputs to insure that they are identical.

A graph of the circuit in the preceding Figure is shown in Figure 14 following:

Figure 14
OTA2 test circuit large signal graph

In Figure 14 we can see that the three outputs are identical. The lower output voltage was set at 0.1mV, and from the graph it can be seen that the output voltage is actually about -0.1 mV for each of the outputs. The upper level output is 2.6 volts, which is the setting for 'vf'. The AC characteristics of this device are of interest. Consequently, Figure 15 following shows the curve of Figure 14 expanded somewhat to show the device behavior about the zero crossing level of the input sine wave.

Figure 15
OTA2 behavior about zero

In Figure 15 the uncompensated purple trace shows the output is slightly different than that of the compensated devices shown in yellow. This is important to note. In a voltage output device, the voltage will be set and the currents will track accordingly. Here the output is a current applied to an impedance (compensating network) and this determines the voltage. Consequently the effects of the compensation network will differ from what one might intuitively expect at first glance.

With a voltage output driven device the output voltage is equal to the quotient of the output voltage and the load impedance. With a current output, the output voltage is equal to the product of the output current and the load impedance. Hence to understand the graph to follow, one must look at the complex admittance of the device to understand what is happening. Before looking at this output, try a mental exercise to try to determine what might be the result. Remember that impedance poles become admittance zeros, and impedance zeros become admittance zeros.

At any rate, Figure 16 shows an AC sweep of the outputs.

Figure 16
OTA2 output AC sweep graph

Now the plot thickens, if you will forgive the pun. The blue and orange curves are the uncompensated DB output and phase in degrees for the uncompensated OTA2 device, while the orange and yellow curves for the compensated OTA2 device.

For the both device, a low frequency gain of 52 DB is shown. This corresponds to the product of the G and delta v and ROUT producing a (2mA)*1*200K output voltage of 400, or a corresponding 52 DB voltage gain. As there is no direct path to ground in the compensating network, the low frequency gain of the compensated network is also 52 DB.

The compensated output curve shape is interesting. There are two output zeros. They cause the output gain to flatten for a bit in a mid-range after an initial drop and then finally start dropping. What this does is to control the device phase shift, and also the gain at and around the switching frequency, making the design fairly robust.

This is really getting into some stuff, which tends to be advanced, even with the voltage driven compensation networks we are all used to. Consequently as most uses of the LT3430 will be somewhat cookbook, and the data sheet provides guidelines for choosing a compensation network it will be best left unsaid at this time.

The last device to be modeled here is the TED circuit. (A NO smooth switch type 1 which was described in a separate article will also be used.) Like the LED circuit, this is based on behavioral device models already in the library. The TED circuit is shown in Figure 17 following:

Figure 17
Trailing Edge Detector (TED) circuit

The circuit is very straightforward in operation. Two pairs of inverters were shown in of the inputs to U6. The purpose is to ensure the trailing edge detector output is long enough for our purposes. A test circuit is shown in Figure 18 following:

Figure 18
TED test Circuit

In Figure 18 we can see the test circuit. U7 is the LED circuit converted into a subcircuit, whose output will be compared to the model to ensure the LED and TED outputs do not coincide and work properly.

Examination of the output(s) for the circuit of Figure 18 reveals that the leading and trailing edge outputs do behave as intended, and that the outputs are distinct. A plot of the TED output is shown in Figure 19 following:

Figure 19
TED test circuit output graph

An astute viewer will note that, whereas the LED output is within the positive pulse output, the TED output is not. This is of no essential importance here as long as the usage of the signals does not, in themselves, limit the maximum modulator pulse width output. Were that the case, one would have to perform more work by adding delays to ensure that the time from the nominal 'SET' to 'RESET' pulses was the maximum attainable pulse width time. This is not the case here.

Now, having all of the essential elements, modeling of the LT3430 can proceed. Note that the values of the devices modeled for use in the final realization have been customized for use in this controller chip. If one were to use them within other chip realizations they might need to be changed for those applications.

The model for the LT3430 is shown in Figure 20 following:

Figure 20
LM3430 model

In this model the various elements are comprised in most instances by behavioral elements that have been presented in my articles in the Resources page, or described herein. It may be seen that the topology is very similar to that of Figure 2 with the exception of the error amplifier. Other differences between this and Figure 1 is that output current sensing is referenced to zero rather than to the input high level VS, and a smooth switch model is used in place of the output transistor.

In most cases the use of a smooth switch in place of an actual device will not affect the results, other than in investigation of the behavior of an actual switching transistor. As we have no details available regarding this device, as we have no controls over its switching behavior in any event, and as details of he device are not know, there really is little else we can do without more information.

The boost function is not modeled, as it is essentially meaningless in this realization, as are the BIAS and SYNC functions.

U6 is the TED, which resets the U4 FF, as well as the ramp output. U10 prevents the controller chip from operating until the input voltage, vs, is greater than 5v. U9 also shuts down the controller chip when the command level is greater than 2.38 v.

The ideal compensation slope has been already determined. The remaining step is to insure that the error amplifier gain is proper for this configuration. As shown in reference 2, the error amplifier should have a minimum gain value at half the switching frequency (100Kc). From Figure 16 we can see the gain at this frequency is about 40dB, which would correspond to a value of about 100.
Figure 21 following is the test circuit for this implementation.

Figure 21
LM3430sm test circuit

It should be noted that in this realization that current senseVam2 is really part of the chip model, and should be imbedded within the chip model. The reason it was not was that this chip model is really not yet finished. Although it seemingly works, I have no experimental results on an overall realization to check the model results against, and to 'tweak' the model with. Consequently it is NOT RECOMMENDED that the circuit of Figure 20 be converted into a device, at least until such time that results are available. Consequently the controller chip model and the test circuit should be treated as a learning exercise until that time.

Bearing that in mind, it is interesting however to perform simulations with the circuit of Figure 21 to learn what we can from it.

Figure 22
Lm3430sm test graph 1

In this unexpanded circuit one can see the result of a step load change provided by controlled source I1 at the output. At t = 1mS, the load is lowered and at t = 2ms reapplied. This is shown in the green trace. Other interesting tests are to ramp up the input voltage source in a realistic manner, and see the effects of the delay in turn on of the controller chip, and to command the controller 'off' by command.

Some sub-harmonic oscillations seem to be present in the output. It is not known if this is 'real', which would not totally surprise me being a one-size-fits-all realization, or if this is a model error at this time. Actually, there is an error in the model, and it is caused by the improper use of the TED circuit. Instead of the TED output turning off the FF, it should be turned off at the end of the compensation ramp - see Figure 8. This could be part of the cause of what seem to be sub-harmonic oscillations.

Inasmuch as the model is tentative at this time, there seems little point in doing much more here. (If a reader is interested, and they provide me with a message with a 'real' email address, not a yahoo or other such email address, I will send them the circuit for them to examine as they wish.) The main utility of the model at this time however is as a learning tool to show some of the thinking in creating a controller chip model. This work was performed under contract; however, time and money did not enable me to finish the model.

Summary:

In this article a preliminary controller chip model was created, along with some other useful elements, which may be used to create other controller chip models. The model here is NOT complete and an error was noted which is present in the model. Nonetheless it illustrates some of the thinking and steps required in creating a controller chip model.

References:

1. Linear Technology LT3430 Data Sheet

2. Unitrode AN U-97, Modeling, analysis and Compensation of the Current-Mode Controller

3. Switch-Mode Power Supply SPICE Cookbook, by Christophe Basso

4. SMPS Simulation with SPICE3, by Stephen M. Sandler

3. Christophe Basso Web site, http://perso.wanadoo.fr/cbasso/Spice.htm