### Timer Models

About the writer: Harvey Morehouse is a contractor/consultant with many years of experience using circuit analysis programs. His primary activities are in Reliability, Safety, Testability and Circuit Analysis. He may be reached at harvey.annie@verizon.net. Simple questions for which I know the answer are free. Complex questions, especially where I am ignorant of the answers, are costly!!!

Summary: Often there is a need for a timer model. The timer should start when an event occurs (a voltage level is reached, or present on a control input.). Most often this timer should be capable of being re-started. Two timers will be created, re-triggerable and non-retriggerable in nature.

A Generic NON-Retriggerable timer model:

The basic model for a timer is a current source charging a capacitor. Inasmuch as:

I = C x dV/dT

It is easy to create a time value by adjusting a current source charging a capacitor, and sensing when the capacitor voltage reaches a pre-determined voltage (time). Inasmuch as the current source will start when time t = 0, a means of starting the timer (preventing the capacitor from charging until a predetermined event has occurred) must be added. This can easily be done by connecting a Normally Closed (NC) switch in parallel with the capacitor that opens when the timer is 'triggered'.

A simple circuit as shown in Figure 1 following will do this, however it is important to note that the triggering signal is somewhat arbitrary. One can make it start when the 'trigger' signal is equal to or greater than a given level, however once specified in a model, unless the models are made unique, additional instances of the model will have identical values and time values. Figure 1
Non-Retriggerable Timer Model

The netlist for the circuit of Figure 1 is:

non-retriggerable timer.ckt
************************
* B2 Spice
************************
* B2 Spice default format (same as Berkeley Spice 3F format)

***** main circuit
I1 0 4 DC 1u
C1 N3 0 1u
R1 4 N3 1K
S1 N3 0 5 0 switch on
R2 N1 0 1K
B1 5 0 v = u(v(n1) - v(n2) - 1) + u(v(n3) - 1e-6)
R3 5 0 1K
V1 N1 0 DC 0 PULSE( 1p 5 0 100u 100u 1p 200u)
.model switch SW vt = .5 vh = 0 ron = 1g roff = 1m
.OPTIONS gmin = 1E-12 reltol = 1E-4 itl1 = 500 itl4 = 500
+ rshunt = 1G
.TRAN 10u 1m 0 1u uic
.IC
.END

Voltage source V1 (and associated ground), provides the switch stimulus for test purposes. Resistor R2 is also added for test purposes, however in a 'real' circuit it is presumed the ground connection will be provided externally and R2 will be unnecessary. The voltage provided by V1 is a triangular voltage.

Switch S1 has what would be the expected 'ON' and 'OFF' resistance values 'exchanged' to account for the presumed library model errors for this device. The switch will toggle when the voltage between nodes N1 and N2 exceed 1V. Once the switch closes, and capacitor C1 starts to charge, this level will logically keep the switch control of generator B1 greater than 1V, regardless of what the voltage between nodes N1 and N2 is.

A graph of the output is shown in Figure 2 following: Figure 2
Non-Retriggerable circuit graph

The graph shows the timer output monotonically increasing once the voltage between nodes N1 and N2 exceeds one volt. If one wishes to detect when a certain time has elapsed after the first event, one can add another nonlinear voltage source to detect when the voltage in volts (time in seconds) has elapsed by making its argument equal to

'v = u(v(n3) - V1'

Where V1 is the value in volts equal to the time in seconds.

Retriggerable Timer circuit:

A retriggerable timer has the same topology as that of Figure 1. The differences are in the generator B1, which controls the switch S1 and hence the discharge of capacitor C1. A netlist for this configuration is as follows:

retriggerable timer.ckt
************************
* B2 Spice
************************
* B2 Spice default format (same as Berkeley Spice 3F format)

***** main circuit
I1 0 4 DC 1u
C1 N3 0 1u
R1 4 N3 1g
S1 N3 0 5 0 switch on
R2 N1 0 1g
B1 5 0 v = u(v(n1) - v(n2) - 1)
R3 5 0 1K
V1 N1 0 DC 0 PULSE( 1p 5 0 100u 100u 1p 200u)
.model switch SW vt = .5 vh = 0 ron = 1g roff = 1m

.OPTIONS gmin = 1E-12 reltol = 1E-4 itl1 = 500 itl4 = 500
+ rshunt = 1G
.TRAN 10u 10m 0 1u uic
.IC
.END

In this realization, when the voltage between nodes N1 and N2 is less than 1V, the switch will close and remain so until the aforementioned voltage is again greater than 1V, causing the voltage across C1 (corresponding to time of the same magnitude) to be accumulated. This is shown in the graph of Figure 3 following: Figure 3
Re-Triggerable Circuit graph

In this re-triggerable realization, the timer starts and then stops, restarting again at the appropriate interval. The elapsed time during any timing interval can be compared to a level to determine if the time before a reset has exceeded a predetermined value.

Re-Triggerable timeouts - Watchdog timer:

Consider a 'watch-dog timer'. In this case the device will repeatedly retrigger following an input, however, a fixed time after the last trigger the device will reset. This is often software driven, in that, if the program does not work as expected - providing periodic resets - an alarm signal will be provided. In this case it is expected that the trigger pulses will be short, and their normal period will be less than the alarm time. This is not too difficult to accomplish with some modifications to the re-triggerable circuit.

Consider the Watchdog Timer circuit of Figure 4 following: Figure 4
Watchdog Timer Circuit realization

The change in this Figure is the addition of source B2, which detects when a given time (voltage across capacitor C2) is exceeded. In this case, B2 generates a voltage when a time of 190us is exceeded. The netlist is as follows:

retriggerable Watchdog timer.ckt
************************
* B2 Spice
************************
* B2 Spice default format (same as Berkeley Spice 3F format)

***** main circuit
I1 0 5 DC 1e-3
C1 N3 0 1e-3 ic = 0
R2 N1 0 1g
B1 N4 0 v =u(v(n1) - v(n2) - 1)
R3 N4 0 1K
V1 N1 0 DC 0 PULSE( 1p 5 0 1p 1p 1u 200u)
R4 N6 0 1K
B2 N6 0 v = u(v(n3)- .00019)
R1 5 N3 1K
S2 N3 0 N4 0 S2_switch off
.model S2_switch SW vt = .5 vh = 0 ron = .1m roff = 1gig

.OPTIONS gmin = 1E-12 reltol = 1E-4 itl1 = 500 itl4 = 500
+ rshunt = 1G
.TRAN 10u 1m 0 1u uic
.IC
.END

In this circuit the generator has been changed to produce approximately 1uS pulses, about 200uS apart. As the detection at N6, the B2 generator, has been set to 190uS (190uV), we should see an output at the end of each ramp during the last 10uS, which the graph of the circuit, shown in Figure 5 following, displays. Figure 5
Watchdog Timer Circuit graph

Note that the output pulse width in this realization has a variable pulse width. This should cause no problems in most cases. More troubling is the rise time of the B2 generator voltage. It appears to default to the step ceiling value in the transient simulation setup, which was left at 1uS. Interestingly enough, the fall time is very rapid. It is presumed that this would cause little problems for timers set for about 1mS or longer detection intervals.

Conclusions:

It is possible to create behavioral logic models that will show elapsed time from a triggering event, as well as to use these models to create more complex timers. These should be useful in a variety of simulations. Note however that these models are neither DC nor AC models, and as a result, linearization of the circuits might fail, either voiding the analysis, or causing unexpected results. Usually this can be worked around by setting the nodes properly, or using a static level or levels in that event.