## Voltage Variable Element Models

### By Harvey Morehouse

**Contents:**

- Variable Transformer
- Variable Resistors (Potentiometers) and Rheostats
- Variable Capacitor: Part 1
- Variable Capacitor: Part 2
- Variable Inductor

### Variable Transformer – A Building Block

*About the writer**:
Harvey Morehouse is a contractor/consultant with many years of experience
using circuit analysis programs. His primary activities are in Reliability,
Safety, Testability and Circuit Analysis. He may be reached at harvey.annie@verizon.net.
Simple questions for which I know the answer are free. Complex questions,
especially where I am ignorant of the answers, are costly!!!*

**Summary**:
In a previous article I showed how to create an ideal transformer.
This element by itself is useful, with or without the addition of
a core element. The ideal transformer itself, if it had a means of
adjusting the turns ratio dynamically, is useful both for investigating
and simulating designs where such a device may be used.

**Ideal
Transformer**:

Ideal Transformer Model: The ideal transformer model was described previously described as having a symbol as follows.

Figure 1

Ideal Transformer Primitive Symbol

The ideal transformer model, slightly modified, was shown as:

Figure 2

Ideal Transformer Primitive Model

The netlist for this device, with a turns ratio of n, from primary to secondary, is:

Circuit1 ************************ * B2 Spice ************************ * B2 Spice default format (same as Berkeley Spice 3F format) ***** main circuit F1 1 2 VAm1 1/n E1 6 4 N1 N2 1/n VAm1 5 6 0 RP 1 2 1e10 RS 5 3 1e-9 R1 2 4 1e10 .END |

The circuit primitive was modified slightly to make it controllable in an analysis, in Figure 3 following:

Figure 3

Modified Variable Transformer Primitive

The output was left isolated to allow the device to be 'rotated', and for generality. Devices E1 and F1 in the original circuit are replaced by non-linear sources. What is needed most generally is not a parameter to be passed but a direct input which, continuously or cycle by cycle, varies D. In that event the output would be a voltage which would, continuously or cycle by cycle, vary the transformer. Thus another pair of input terminals was provided where the 'D' level could be used as an input. It is presumed that the range of this input was somewhere between 0 and less than unity. The corresponding netlist becomes:

************************ * B2 Spice ************************ * B2 Spice default format (same as Berkeley Spice 3F format) ***** main circuit RP N1 N2 1e10 RS 6 N3 1e-9 R1 N5 N6 1Meg VAm1 10 6 0 B2 N1 N2 i=i(vam1)*v(5,6) B1 10 N4 v=v(1,2)*V(5,6) .END |

Note that the node numbers in the above will not be correct if and when grounds are used in the circuit. A suitable symbol is required for this device. One like the following may be used.

A test circuit was provided for this primitive. This is shown in Figure 5 following:

Figure 5

Variable Transformer test circuit

A netlist for the test circuit is as shown as follows:

*
B2 Spice |

This circuit was analyzed with a parameter sweep of voltage source V2. V2 was varied between 0 and 1 in steps of 0.25V. A plot of this simulation is shown in Figure 6.

Figure 6

Transient Parameter Sweep

**Conclusions:**

The preceding plot shows that a variable transformer can be created, which can be dynamically modified by a control voltage between zero and one volts. Later, time permitting, other articles will show how this may be used in the simulation of Switching Mode Power Supplies.

### Simple Potentiometers and Rheostats

**Summary**:
The makers of B2SPICE have provided a variable resistor model (not in
the library) in a file entitled pot.ckt. Unfortunately, it is misnamed.
What is provided is a simple variable resistor model which is more akin
to a rheostat than a potentiometer (pot). In this article a simple potentiometer
model is created which can be used also as a rheostat as well.

**Basics:**
A potentiometer is a variable, tapped resistor. Normally a voltage (or
current) is applied through the device, from one end to the other. The
tap connects a portion of the resistance as an output, providing an
output that is a fraction of the voltage across the device. The tap
may be connected to one end of the device or the other, causing the
total device resistance to vary from essentially zero ohms to the full
resistance of the device (or the converse, depending on the end the
tap is connected to), depending on the position of the tap.

There are complications, however. Some pots are 'infinite resolution'. By this it is meant that the pot slider or tap is designed such that a smooth selection change is provided for the tap position change. (Of course there is usually a practical limit to the physical variability of the tap, limited to perhaps a degree or so of rotation of the tap selection screw.) Other pots, particularly wire-wound versions that are not infinite resolution types, will have an inherit limit to the effective tap control to a value equal to the turn to turn resistance of the pot winding. Vibration can affect the tap setting as well, however for such pots, the usual fix is to cement the adjustment screw to prevent its changing after it is positioned.

Another problem is that of potentiometer resistance variation over life and with temperature. It is expected that variations would be almost identical with life over the two equivalent resistances in a 'real' pot, hence the voltage divisions would be nearly unchanged. A problem would be disproportionate heating in the two sections of the pot, mostly caused by loading of the pot. But this would be a second order effect at most. It is expected then that the only variation of consequence would be the end-to-end resistance variation, and proportionate changes in each of the two equivalent resistances modeling the pot.

In some pots, the taper, or change of resistance with the tap position, is not linear. A common type is a log taper, in which the resistance changes logarithmically with tap position.

The most significant problem is the controlling voltage. One would like to provide a control voltage with a range from zero to one volt, corresponding to a 0% to a 100% pot variation. Such a control might not be physically viable in many circuits if one attempts to use an existing node voltage as a control. As an example, consider a circuit where the controlling voltage might be of the opposite polarity, of a range from v1 to v2 volts corresponding to 0% to 100% setting. Moreover, consider the case where v1 is negative and v2 is positive. Now of course one could use external circuitry to condition the control voltage, however it would be nice if one could imbed these conditions into the model to make it most general.

Now of course if the controlling voltage is a circuit voltage, as opposed to using an 'optimize' function (if provided), then it must be connected in such a manner to provide negative feedback, so that the pot is properly adjusted.

Are these considerations important? They could be. One uses a pot most often to adjust a circuit to a given DC or AC operating point. E.G., setting a voltage or a gain to null out errors or voltage divider errors or resistance values to adjust a gain. One could run a simulation for a given set of conditions to determine the appropriate setting (control voltage value) for a pot, and then fix the control voltage. One then would perform the desired analyses for this case, repeating it as required for different conditions.

It would
be very nice IF one could __ automatically__, perhaps in a
Monte Carlo or AC or DC analysis, to generate a given set of STARTING
Beginning-Of-Life (BOL) conditions or component variations, use these
to determine and generate a pot setting, and then, using End-Of-Life
(EOL) variations from these BOL conditions simulate the circuit. Some
higher priced products allow one to do this. Unfortunately this is not
the case in B2SPICE. Perhaps at some time this will be so, but to do
this would require a 'scripting' or 'batch' mode of operation.

The problem of HOW one controls/adjusts the pot, what exact setting to use, how to vary this over several simulations is not easily handled. The same problem is present whenever there are Select-At-Test resistors used in a design, for their usage present many of the same problems. But this is more of a design problem, certainly an analysis problem, out of scope for this article that is about modeling of a pot.

**Modeling
approach:** In this paper, we shall only be modeling the simplest
of pots. They shall be infinite resolution models, with no limits on
tap control other than from zero to 100% control.

But first
some explanations are in order. One **may** create a resistor without
using a primitive resistance element. This is done by means of one or
two means. Consider Ohm's law. The normal formulation is:

i = e/R

Rewriting, R = i/e

What this means is that, between two nodes, the effective resistance R is determined by the ratio of current to voltage. We can use this in two ways. We can sense the current through the nodes and provide a voltage generator in opposition to the applied voltage source that is equal to the product of that current and the desired resistance value. Alternately, we can measure the voltage across the two nodes and use a current source to force the current from one node to the other to be the quotient of the voltage across the nodes and the desired resistance value. Often both methods are used to create two pot models within a library. Why is this?

If one uses the voltage source method, care must be taken to ensure the device is never connected directly across a voltage source, as convergence problems can occur UNLESS a resistance is provided in series with the voltage source. Otherwise a loop of three voltage sources can occur. If one used the current source method, similar convergence problems can exist. We will use the voltage source method, however, we will add a very small resistance in series with the pot, and at the tap to preclude problems. This will of course, cause the model to be ever so slightly in error, but be of no real significance in all but a few contrived cases.

**Circuit
Test Model:**

The proposed pot model, imbedded in a simple test circuit, is shown in Figure 1 following:

Figure 1

Simple Potentiometer - 1

The netlist for this circuit is shown in the following:

Simple pot 1.ckt

************************

* B2 Spice

************************

* B2 Spice default format (same as Berkeley Spice 3F format)

***** main circuit

R4 N2 0 1g

R1 N1 5 1e-2

R3 N4 0 1K

R2 11 N2 1e-6

V1 N1 0 DC 10

B1 5 7 v =i(vam1)*10000*(1-v(n3))

V2 N4 0 DC 10 SIN( .5 .5 1k 0 0)

VAm2 10 0 0

B2 11 10 v =i(vam2)*10000*v(n3)

VAm1 7 11 0

.OPTIONS gmin = 1E-12 reltol = 1E-4 itl1 = 500 itl4 = 500

+ rshunt = 1G

.TRAN 10u 2m 0 1u

.IC

.END

In this circuit sources V1 and V2, and the ground reference are provided for test purposes. R3 is added to allow the input voltage (provided by source V2) a return path should a voltage source be directly connected to nodes N4 and N5. R4 was added to suppress SPICE warnings about an unconnected node. Neither R1, R2 nor R3 has an appreciable effect on any circuit it may be used in. The 'guts' of the model are elements R1, R2, nonlinear voltage sources B1 and B2, and ammeters Vam2 and Vam2. The resistance of the potentiometer is 10K.

A simulation of the circuit of Figure 1 is provided in Figure 2 following:

Figure 2

Simple Potentiometer - 1 circuit graph

Although it is hard to see, the N2 and N4 voltages track as expected. The current through Source V1 (which is the negative of the current seems distorted, however, noting the axis values shown as unchanging 1mA, reflect the slight computational errors in the overall impedance of the pot model. As the control voltage is set to vary between zero and 1V in a sinusoidal value, the voltage at N2 does also.

**Pot
model:**

The pot model, stripped of the test elements, is shown in Figure 3 following:

Figure 3

Simple pot model

The netlist for this model is as follows:

Simple pot 2.ckt

************************

* B2 Spice

************************

* B2 Spice default format (same as Berkeley Spice 3F format)

***** main circuit

R1 N1 4 1e-3

R3 N4 N5 1K

R2 11 N2 1e-6

B1 4 7 v =i(vam1)*10000*(1-v(n4) - v(n5))

VAm2 9 N3 0

B2 11 9 v =i(vam2)*10000*(v(n4) - v(n5))

VAm1 7 11 0

.OPTIONS gmin = 1E-12 reltol = 1E-4 itl1 = 500 itl4 = 500

+ method = gear rshunt = 1G

.TRAN 10u 2m 0 1u

.IC

.END

Note that
the nodes have changed slightly from those in the preceding circuit.
Also, resistor R3 could be changed in value if desired. No ground is
present, as it is expected that it will be provided by the circuit this
pot model is imbedded within.

**Conclusions:**

A simple
three terminal pot model has been created. This circuit is usable for
many simulations.

### Variable Capacitor: Part 1

**Summary**:
In previous articles I showed how to create a variable transformer,
as well as a variable resistor. This article will show how to create
a voltage-variable capacitor.

**Voltage
variable capacitor:**

It would seem trivial to create a voltage-variable capacitor. One could just pass parameter variables to a capacitor's capacitance. Simple …… or is it?

If one does this, one creates a model that will exhibit steps in voltage across the capacitor if the capacitor value is changed. This is neither desired nor correct. This occurs due the model error, as a result of misusing/misapplying the fundamental capacitor equations.

The defining equation for a capacitor is:

I(t) = C(v2(t)) * dv/dt

Clearly, the capacitance is a variable, a function of the controlling voltage. The other 'v' in dv/dt refers to the voltage applied to the capacitor. To keep them separate, we designate the controlling voltage as v2(t). Solving for dv/dt,

dv/dt = i(t)/C(v2(t))

Integrating both sides results in:

v = integral [i(t)/C(v2(t))]

Let the value of the capacitance C(v2(t)) be Co + v2(t)*Co, where Co is the value of the capacitor with va(t) = 0. It is convenient to nominally define the control voltage limits to between zero and one volts. This would however limit the capacitance variation to 2 * Co. One could allow va(t) to vary greater than 1 volt. We can get a little more flexibility by introducing another variable, k. The defining equation for C(v2(t)) becomes:

C(v2(t)) = Co + k*v2(t)*Co

'k' could of course be fractional. Suppose the maximum v2(t) were 5V, however, if it were desired to make the maximum capacitance be perhaps 3.5 times the zero voltage value, k would be set to a value equal to 3.5/5 or 0.7.

**Modeling:**

A model embedded in a test circuit is shown in Figure 1 following:

Figure 1

Voltage variable capacitor test circuit

A netlist for this circuit is:

Circuit1

************************

* B2 Spice

************************

* B2 Spice default format (same as Berkeley Spice 3F format)***** subcircuit definitions**-- Continuous Filtering Function Macromodel --**

.SUBCKT cffm 10 30 20

* Node 10= Input, Node 30= Output, Node 20= GND

RIN 10 20 1.000000e-003

BEIN 100 0 V= V(10,20) * 1.000000e+000 - V(101) * 0.000000e+000

REI 100 0 1

G1 0 101 100 0 1

R1 101 0 1T

C1 101 0 1

BESO 102 0 V= V(100) * 0.000000e+000 + V(101) * 1.000000e+000

ROT 102 30 1.000000e-003

RDY 30 0 1T

.ENDS cffm

***** main circuit

VAm1 N3 5 0

B1 5 0 v=v(n4,0)

B2 6 0 v = I(Vam1) / (1e-6+1e-6*1*v(n1,n2))

V3 7 0 DC 10

V1 8 0 DC 10

R1 N3 8 10K

R2 N4 0 1Meg

R3 N1 0 1G

V2 N1 0 DC 0 PULSE( 0 2 5m 1p 1p 100m 1)

XX1 6 N4 0 cffm

R4 7 N5 10K

C1 N5 0 1u

.OPTIONS gmin = 1E-12 reltol = 1E-4 itl1 = 500 itl4 = 500

+ rshunt = 1G

.TRAN 10u .1 0 10u uic

.IC

.END

A perhaps unfamiliar block in the model is the continuous filtering function. This block is used as a LaPlace function integrator. Its transfer function is '1/s', where 's' is the Laplace operator. The control voltage is a pulse with an amplitude of 2V, starting at 5 mS and lasting for 100 mS.

A graph of the output with the values of 'Co' to be simulated as 1uFd, k =1, and 10V DC in series with a resistance of 10K applied to the 'capacitor' is shown in Figure 2.

Figure 2

Voltage variable capacitor test circuit

The 'pink' trace is the 'reference' capacitor. The test circuit 'orange' trace and the reference trace coincide until about 5 mS, when the test capacitor value changes for the duration of the trace. The output trace shows no abrupt jumps, as should be the case.

It is left as an exercise for the reader to create a parameterized subcircuit model for this device as well as an appropriate symbol, passing it values for Co and k.

**Summary:**

A voltage
variable capacitor model has been created. The B2 device equation may
be changed to reflect devices that operate in other manners, such as
perhaps a square law function of voltage.

### Variable Capacitor: Part 2

**Summary**:
In previous article I showed how to create a voltage-variable capacitor
(VVC). I had a need of a voltage variable capacitor for use in an averaged
Current Mode SMPS device model. The circuit used a VVC, but did not
do so correctly.

*This
article extends the analysis with more testing and prepared a circuit
in B2SPICE version 5 format.*

**Voltage
variable capacitor:**

It would seem trivial to create a voltage-variable capacitor. One could just pass parameter variables to a capacitor's capacitance. Simple …… or is it?

If one does this, one creates a model which will exhibit steps in voltage across the capacitor if the capacitor value is changed. This is neither desired nor correct. This occurs due the model error, as a result of misusing/misapplying the fundamental capacitor equations.

The defining equation for a capacitor is:

I(t) = C(v2(t)) * dv/dt

Clearly, the capacitance is a variable, a function of the controlling voltage. The other 'v' in dv/dt refers to the voltage applied to the capacitor. To keep them separate, we designate the controlling voltage as v2(t). Solving for dv/dt,

dv/dt = i(t)/C(v2(t))

Integrating both sides results in:

v = integral [i(t)/C(v2(t))]

The circuit in question solved (incorrectly) for the equation:

v = integral [i(t)]/C(v2(t))

In part, for this reason, the circuit would not converge well in a transient analysis where mode switching occurred, and even where it might, the results could be in error. This solution would in effect cause discontinuous jumps in capacitor current when the value

The circuit would simulate correctly in an AC swept frequency mode, however, as we know, SPICE performs an AC analysis by first obtaining a DC operating point. This is done by opening all capacitors, shorting all inductors and obtaining a DC operating point. Next, the circuit is linearized about that operating point.

Now the value of the resonating capacitor used to create the effects of sampled data gain peaking is of course determined by equations, used to drive a voltage or current source dependent on the modeling, and thus is determined even in a DC operating point solution. However, the value of capacitance is determined by equations, and the solution will be determined by the circuit being in CCM or DCM.

This value will either be negligibly small, or of a calculated magnitude to illustrate the effects of sampling at a rate exceeding twice the twice the switching frequency. This subject and SMPS modeling are not germane to this article, except to illustrate that there is a practical application for such a model.

Now the whole nature of these phantom effects, right-hand half-plane zeros and poles is fairly well described in the literature BUT for one detail. Consider a capacitor which suddenly appears due to CM CCM mode operation, acquires a charge, and then disappears when the CCM mode is exited. Where did the charge go?

It is assumed herein, from an engineering and a circuit viewpoint, that the VVC modeling of such a device will, conserving charge, properly or at least sufficiently accurately allow a CCM model to be prepared usable in AC and DC simulations. That is the ultimate end of the work shown here.

**Modeling:**

The previous voltage variable capacitor paper showed a model embedded in a test circuit. A similar circuit is shown in Figure 1 following:

Figure 1

Voltage variable capacitor test circuit

A perhaps unfamiliar block in the model is the continuous filtering function. This block is used as a Laplace function integrator. Its transfer function is '1/s', where 's' is the Laplace operator. The control voltage is a pulse train with amplitude of 1V.

ID1 is an ideal diode device used to present a pulsating DC voltage to the load.

The B2 generator uses the equation:

v = I(Vam1) / (1e-12+v(n1,n2)*1e-6)

Whereas the B1 generator uses:

v=v(n4,0)

The B2 equation has two denominator values, one the capacitance when the v(n1,n2) value is (assumed one) of 1uF, and otherwise when v(n1,n2) is null of 1uuF. These values could be changed as required or passed as parameters. Or, one could make the control voltage variable, or alter the denominator equation to suit some need.

Figure 2

Voltage variable capacitor test circuit

In Figure 2 can be seen the effects of the capacitor switching. The Am1 current is small when the capacitance is 1p, and changes to an RC change and discharge current when the input causes it to appear as 1uF. Am2 shows the resistor current is added to the capacitor current. During the time when the capacitor is at 1uF, the RC smoothing may be seen.

**Summary:**

A voltage
variable capacitor model has been created. The purpose of so doing was
to create a replacement, conservative, capacitor model for use in a
SMPS CM averaged converter model.

### Variable Inductor

**Summary**:
In previous articles I showed how to create a variable transformer,
as well as a variable resistor, and a variable inductor. This article
will show how to create a voltage-variable inductor.

**Voltage
variable inductor:**

It would seem trivial to create a voltage-variable inductor. One could just pass parameter variables to an inductor's inductance. However, just as in the case of the variable capacitor, one must first look to the defining equations for an inductor.

eL(t) = L(vc(t)) * d(iL(t))/dt

We can divide both sides by L(vc(t)) resulting in only in a current dependent derivative on the right hand side. Then, interchanging left and right hand sides of the equality and integrating both sides, we get the result:

iL(t) = integral [eL(t)/ L(vc(t))]

This is similar to the result we had for the capacitor. In this case the current will not abruptly change through the inductor, whereas for the capacitor, the voltage will not abruptly change.

Clearly, the inductance is a variable, a function of the controlling voltage, which is itself a function of time.

Let the value of the capacitance L(vL(t)) be L0 + vc(t)* L0, where Lo is the value of the inductance with vL (t) = 0. It is convenient to nominally define the control voltage limits to between zero and one volts. This would however limit the inductance variation to 2 * Lo. One could allow va(t) to vary greater than 1 volt. We can get a little more flexibility by introducing another variable, k. The defining equation for L(vc(t)) becomes:

L(vc(t)) = L0 + k*vc(t)* L0

'k' could of course be fractional. Suppose the maximum vc(t) were 5V, however, if it were desired to make the maximum inductance be perhaps 3.5 times the zero voltage value, k would be set to a value equal to 3.5/5 or 0.7.

Were vc to have a maximum voltage of perhaps 5V, and the desired inductance at that level to be perhaps 1/50 * L0, then 1 + k*vc(t) minimum would be equal to 1 + k * 5 = 1/50. Solving this for k produces a value of -0.196. Now of course we could accomplish the same thing by letting in this case vc vary from zero to -5V, in which case k would equal +0.196.

**Modeling:**

A voltage variable inductor model embedded in a test circuit is shown in Figure 1 following:

Figure 1

Voltage variable inductor test circuit

A netlist for this circuit is:

Circuit1

************************

* B2 Spice

************************

* B2 Spice default format (same as Berkeley Spice 3F format)***** subcircuit definitions**-- Continuous Filtering Function Macromodel --**

.SUBCKT cffm 10 30 20

* Node 10= Input, Node 30= Output, Node 20= GND

RIN 10 20 1.000000e+006

BEIN 100 0 V= V(10,20) * 1.000000e+000 - V(101) * 0.000000e+000

REI 100 0 1

G1 0 101 100 0 1

R1 101 0 1T

C1 101 0 1

BESO 102 0 V= V(100) * 0.000000e+000 + V(101) * 1.000000e+000

ROT 102 30 1.000000e-003

RDY 30 0 1T

.ENDS cffm

***** main circuit

VAm1 5 N3 0

B1 N3 0 i = v(n4,0)

B2 6 0 v = V(n3,n6) / (1+1*1*v(n1,n2))

V3 7 0 DC 10

V1 8 0 DC 10

R1 5 8 1K

R2 N4 0 1Meg

R3 N1 0 1G

V2 N1 0 DC 0 PULSE( 0 1 1m 1p 1p 100m 1)

XX1 6 N4 0 cffm

R4 7 N5 1K

L1 N5 0 1 ic = 0

.OPTIONS gmin = 1E-12 reltol = 1E-4 itl1 = 500 itl4 = 500

+ rshunt = 1G

.TRAN 10u .01 0 100u uic

.IC

.END

A perhaps unfamiliar block in the model is the continuous filtering function, cffm. This device is found under the sources category, for some strange reason. This block is used as a LaPlace function integrator. Its transfer function is '1/s', where 's' is the Laplace operator. The control voltage is a pulse with amplitude of 2V, starting at 5 mS and lasting for 100 mS.

A graph of the output with the values of 'Lo' to be simulated as 1Hy, k =1, vc a 1V, 1mS delayed step of 10V DC in series with a resistance of 1K applied to the 'inductor', is shown in Figure 2.

Figure 2

Voltage variable capacitor test circuit

The 'red' trace is the 'reference' inductor. The inductor voltage test circuit 'blue' trace and the reference circuit trace of inductor voltage coincide until 1 mS, when the test inductor value changes for the duration of the trace. The output trace shows no abrupt jumps, as should be the case.

It is left as an exercise for the reader to create a parameterized subcircuit model for this device as well as an appropriate symbol, passing it values for Lo and k.

**Summary:**

A voltage
variable capacitor model has been created. Note that the inductance
is a function of time, and NOT inductor current. A model of an inductor
whose inductance is a function of current (flux) is more complex, and
has been presented in another article.