B2.Spice A/D Netlist Files



For the hardcore Spice users out there (and you know who you are), the "Netlist" feature allows you to get down and dirty with the Spice language. Convert existing circuits to the Netlist format, import Netlist files, or create a circuit from scratch through the Netlist. And just like the schematics, you can run all supported simulations through the netlist files. And with B2.Spice's intelligent Netlists, you can specify plots and table columns by using the standard .plot and .print commands. Zero-current current sources are interpreted as voltmeters, and zero-voltage voltage sources are interpreted as ammeters. These are automatically plotted in the graphs.

Pretty schematics? Strictly for amateurs. Real engineers do it through Netlists!

 

Osc-OPA.ckt
************************
* B2 Spice
************************
* B2 Spice default format (same as Berkeley Spice 3F format)

***** subcircuit definitions

*$
*//////////////////////////////////////////////////////////////////////
* (c) national semiconductor, inc.
* models developed and under copyright by:
* national semiconductor, inc.
*/////////////////////////////////////////////////////////////////////
* legal notice: this material is intended for free software support.
* the file may be copied, and distributed; however, reselling the
*  material is illegal
*//////////////////////////////////////////////////////////
*lm741 operational amplifier macro-model
*//////////////////////////////////////////////////////////
*
* connections:      non-inverting input
*                   |   inverting input
*                   |   |   positive power supply
*                   |   |   |   negative power supply
*                   |   |   |   |   output
*                   |   |   |   |   |
*                   |   |   |   |   |
.subckt lm741_ns    1    2   99   50   28
*
*features:
*improved performance over industry standards
*plug-in replacement for lm709,lm201,mc1439,748
*input and output overload protection
*
****************input stage**************
*
ios 2 1 20n
*^input offset current
r1 1 3 250k
r2 3 2 250k
i1 4 50 100u
r3 5 99 517
r4 6 99 517
q1 5 2 4 qx
q2 6 7 4 qx
*fp2=2.55 mhz
c4 5 6 60.3614p
*
***********common mode effect***********
*
i2 99 50 1.6ma
*^quiescent supply current
* eos 7 1 poly(1) 16 49 1e-3 1
beos 7 1 v = 1e-3 + 1 * v(16, 49)
*input offset voltage.^
r8 99 49 40k
r9 49 50 40k
*
*********output voltage limiting********
v2 99 8 1.63
d1 9 8 dx
d2 10 9 dx
v3 10 50 1.63
*
**************second stage**************
*
eh 99 98 99 49 1
g1 98 9 5 6 2.1e-3
*fp1=5 hz
r5 98 9 95.493meg
c3 98 9 333.33p
*
***************pole stage***************
*
*fp=30 mhz
g3 98 15 9 49 1e-6
r12 98 15 1meg
c5 98 15 5.3052e-15
*
*********common-mode zero stage*********
*
*fpcm=300 hz
g4 98 16 3 49 3.1623e-8
l2 98 17 530.5m
r13 17 16 1k
*
**************output stage**************
*
* f6 50 99 poly(1) v6 450u 1
bf6 50 99 i = 450e-6 + 1 * i(v6)
e1 99 23 99 15 1
r16 24 23 25
d5 26 24 dx
v6 26 22 0.65v
r17 23 25 25
d6 25 27 dx
v7 22 27 0.65v
v5 22 21 0.18v
d4 21 15 dx
v4 20 22 0.18v
d3 15 20 dx
l3 22 28 100p
rl3 22 28 100k
*
***************models used**************
*
.model dx d(is=1e-15)
.model qx npn(bf=625)
*
.ends


***** main circuit
R4 1  2  10K 
R3 1  0  1K 
R1 2  3  16K 
R2 4  0  16K 
C1 3  4  0.01u 
C2 4  0  0.01u 
IVout 2  0 0
V2 0  5 DC 12 
V1 6  0 DC 12 
X 4  1  6  5  2 lm741_ns


.OPTIONS  itl4 = 200 
.TRAN  100u 10m 0 100u uic
.IC 
.END